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full speed usb, 16 k isp flash mcu family c8051f320/1 rev. 1.4 8/09 copyright ? 2009 by silicon laboratories c8051f32x analog peripherals - 10-bit adc ? up to 200 ksps ? up to 17 or 13 external single-ended or differential inputs ? vref from external pin, internal reference, or vdd ? built-in temperature sensor ? external conversion start input - two comparators - internal voltage reference - por/brown-out detector usb function controller - usb specification 2.0 compliant - full speed (12 mbps) or low speed (1.5 mbps) o peration - integrated clock recovery; no external crystal required for full speed or low speed - supports eight flexible endpoints - 1 kb usb buffer memory - integrated transceiver; no external resistors required on-chip debug - on-chip debug circuitry facilitates full speed, non-intrusive in-system d ebug (no emulat or required) - provides breakpoints, single stepping, ? inspect/modify memory and registers - superior performance to emulation systems using ice-chips, target pods, and sockets voltage regulator input: 4.0 to 5.25 v high speed 8051 c core - pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks - up to 25 mips throughput with 25 mhz clock - expanded interrupt handler memory - 2304 bytes internal ram (1k + 256 + 1k usb fifo) - 16 kb flash; in-system programmable in 512-byte sectors digital peripherals - 25/21 port i/o; all 5 v tolerant with high sink current - hardware enhanced spi?, enhanced uart, and s mbus? serial ports - four general purpose 16-bit counter/timers - 16-bit programmable counter array (pca) with five capture/compare modules - real time clock mode usi ng external clock source and pca or timer clock sources - internal oscillator: 0.25% accuracy with clock recovery enabled. supports all usb and uart modes - external oscillator: crystal, rc, c, or clock ? (1 or 2 pin modes) - can switch between clo ck sources on-the-fly; ? useful in power saving strategies rohs compliant packages - 32-pin lqfp (c8051f320) - 28-pin qfn (c8051f321) temperature range: ?40 to +85 c analog peripherals 10-bit 200 ksps adc 16 kb isp flash 2304 b sram por debug circuitry 16 interrupts 8051 cpu (25mips) digital i/o precision internal oscillator high-speed controller core a m u x crossbar + - wdt + - usb controller / transceiver uart smbus pca timer 0 timer 1 timer 2 timer 3 spi port 0 port 1 port 2 port 3 temp sensor vreg vref
c8051f320/1 2 rev. 1.4
rev. 1.4 3 c8051f320/1 table of contents 1. system overview............ ............................................................................. ........... 15 1.1. cip-51? microcontroller core.. ............................................................. ........... 18 1.1.1. fully 8051 compatible...... ............................................................. ........... 18 1.1.2. improved throughput ............ ........................................................ ........... 18 1.1.3. additional features .......... ............................................................. ........... 18 1.2. on-chip memory......... ........................................................................... ........... 19 1.3. universal serial bus controll er ................. ............................................. ........... 20 1.4. voltage regulator ....... ........................................................................... ........... 21 1.5. on-chip debug circuitr y.................... .................................................. ............. 21 1.6. programmable digital i/o and crossbar ............... ................................. ........... 22 1.7. serial ports ............ ................................................................................ ........... 23 1.8. programmable counter array ... ............................................................. ........... 23 1.9. 10-bit analog to digital conver ter.................... .............. ............... ........... ......... 24 1.10.comparators............. ............................................................................. ........... 25 2. absolute maximum ratings ........ ............................................................... ........... 27 3. global electrical characteristic s .................. ............................................. ........... 28 4. pinout and package definitions..... ............... ............................................. ........... 30 5. 10-bit adc (adc0).......... ............................................................................. ........... 39 5.1. analog multiplexer ...... ........................................................................... ........... 40 5.2. temperature sensor ............ .................................................................. ........... 41 5.3. modes of operation ............. .................................................................. ........... 43 5.3.1. starting a conversion....... ............................................................. ........... 43 5.3.2. tracking modes................ ............................................................. ........... 44 5.3.3. settling time r equirements ................ .......................................... ........... 45 5.4. programmable window detector ........................................................... ........... 50 5.4.1. window detector in sing le-ended mode .......... ............................ ........... 52 5.4.2. window detector in differential mode..... .............. ............... ........... ......... 53 6. voltage reference .......... ............................................................................. ........... 55 7. comparators .............. ................................................................................ ........... 57 8. voltage regulator (reg0)......... .................................................................. ........... 67 8.1. regulator mode selectio n................ ........................................................ ......... 67 8.2. vbus detection .......... ........................................................................... ........... 67 9. cip-51 microcontroller ............. .................................................................. ........... 71 9.1. instruction set ........... ............................................................................. ........... 72 9.1.1. instruction and cpu timing .. ........................................................ ........... 72 9.1.2. movx instruction and program memory ... ................................. ............. 73 9.2. memory organization........... .................................................................. ........... 77 9.2.1. program memory.............. ............................................................. ........... 77 9.2.2. data memory........ ......................................................................... ........... 78 9.2.3. general purpose registers ........................................................... ........... 78 9.2.4. bit addressable lo cations.............. ............................................... ........... 78 9.2.5. stack ................. ........................................................................... ........... 78 9.2.6. special function registers. ........................................................... ........... 79
c8051f320/1 4 rev. 1.4 9.2.7. register descriptions ....... ............................................................. ........... 83 9.3. interrupt handler ................ .................................................................. ............. 87 9.3.1. mcu interrupt sources a nd vectors ............ ................................. ........... 87 9.3.2. external interrupts .......... ............................................................... ........... 88 9.3.3. interrupt priorities ........ .................................................................. ........... 88 9.3.4. interrupt latency .............. ............................................................. ........... 89 9.3.5. interrupt register descrip tions.............. .......................................... ......... 90 9.4. power management modes ........... ........................................................ ........... 97 9.4.1. idle mode............ ........................................................................... ........... 97 9.4.2. stop mode ...................... ............................................................... ........... 97 10. reset sources .... ............... ......................................................................... ........... 99 10.1.power-on reset ....... ............................................................................. ......... 100 10.2.power-fail reset / vd d monitor ................. .......................................... ......... 101 10.3.external reset .......... ............................................................................. ......... 102 10.4.missing clock detector reset ... ............... ............................................. ......... 102 10.5.comparator0 reset ............. .................................................................. ......... 102 10.6.pca watchdog timer reset ..... ............... ............................................. ......... 102 10.7.flash error reset ..... ............................................................................. ......... 102 10.8.software reset ......... ............................................................................. ......... 103 10.9.usb reset................ ............................................................................. ......... 103 11. flash memory .......... .................................................................................. ......... 106 11.1.programming the flash memory .......................................................... ......... 106 11.1.1.flash lock and key functi ons ................ .............. ............... .................. 106 11.1.2.flash erase procedure ...... ........................................................... ......... 106 11.1.3.flash write procedure ..... ............................................................. ......... 107 11.2.non-volatile data storage ... .................................................................. ......... 107 11.3.security options ....... ............................................................................. ......... 108 11.4.flash write and erase guidelines ............... .......................................... ......... 110 11.4.1.vdd maintenance and the vd d monitor .......... ............................ ......... 110 11.4.2.16.4.2 pswe maintenance ... ........................................................ ......... 111 11.4.3.system clock ....... ......................................................................... ......... 111 12. external ram ........... .................................................................................. ......... 114 12.1.accessing user xram .... ...................................................................... ......... 114 12.2.accessing usb fifo s pace ....................... .......................................... ......... 114 13. oscillators ................ .................................................................................. ........... 116 13.1.programmable internal oscilla tor .................... .............. ............... .................. 116 13.1.1.programming the inter nal oscillator on c8051f320/ 1 devices ............. 117 13.1.2.internal oscillator susp end mode ................ ................................. ......... 118 13.2.external oscillator drive circuit................ ............................................. ......... 119 13.2.1.clocking timers direct ly through the exte rnal oscillator.... .................. 119 13.2.2.external crystal example. ............................................................. ......... 119 13.2.3.external rc example....... ............................................................. ......... 120 13.2.4.external capacitor exampl e................ .......................................... ......... 120 13.3.4x clock multiplier .... ............................................................................. ......... 122 13.4.system and usb clock selection ............ ............................................. ......... 123
rev. 1.4 5 c8051f320/1 13.4.1.system clock selection ... ............................................................. ......... 123 13.4.2.usb clock selection ........ ............................................................. ......... 123 14. port input/output ....... ................................................................................ ......... 126 14.1.priority crossbar decoder ... .................................................................. ......... 128 14.2.port i/o initialization ........ ...................................................................... ......... 130 14.3.general purpose port i/o .... .................................................................. ......... 132 15. universal serial bus controller (usb)............. .......................................... ......... 139 15.1.endpoint addressing .... ......................................................................... ......... 140 15.2.usb transceiver ................. .................................................................. ......... 140 15.3.usb register access .......... .................................................................. ......... 142 15.4.usb clock configuration........ ............................................................... ......... 146 15.5.fifo management .......... ...................................................................... ......... 147 15.5.1.fifo split m ode .................... ........................................................ ......... 147 15.5.2.fifo double buffering ....... ........................................................... ......... 148 15.5.3.fifo access ........ ......................................................................... ......... 148 15.6.function addressing............ .................................................................. ......... 149 15.7.function configuration and cont rol ................................................................ 149 15.8.interrupts ........... .................................................................................. ........... 152 15.9.the serial interface engine . .................................................................. ......... 157 15.10.endpoint0 ................. ........................................................................... ......... 157 15.10.1.endpoint0 setup transacti ons .............. ................................. ........... 158 15.10.2.endpoint0 in transactions... ................. .............. ............... .................. 158 15.10.3.endpoint0 out tran sactions................ .............. ............... .................. 159 15.11.configuring endpoints1?3 ...... ............................................................. ......... 161 15.12.controlling endpoints1 ?3 in............... ................................................. ......... 161 15.12.1.endpoints1-3 in in terrupt or bulk mode .............. ............... .................. 161 15.12.2.endpoints1-3 in isochro nous mode............. ............................... ......... 162 15.13.controlling endpoints1?3 out.... ........................................................ ......... 164 15.13.1.endpoints1-3 out interrupt or bulk mode.......... ............... .................. 164 15.13.2.endpoints1-3 out isochronous mode....... ................................. ......... 165 16. smbus ................. ......................................................................................... ......... 169 16.1.supporting documents ............. ............................................................. ......... 170 16.2.smbus configuration... ............... ........................................................... ......... 170 16.3.smbus operation ....... ........................................................................... ......... 170 16.3.1.arbitration......... ............................................................................. ......... 171 16.3.2.clock low extension........ ............................................................. ......... 171 16.3.3.scl low timeout.... ...................................................................... ......... 171 16.3.4.scl high (smbus free) ti meout .............. ................................. ........... 172 16.4.using the smbus........ ........................................................................... ......... 172 16.4.1.smbus configuration regist er................ .............. ............... .................. 173 16.4.2.smb0cn control register . ........................................................... ......... 176 16.4.3.data register ....... ......................................................................... ......... 179 16.5.smbus transfer modes... ...................................................................... ......... 180 16.5.1.master transmitter mode .. ............... ............................................. ......... 180 16.5.2.master receiver mode .............. .................................................. ........... 181
c8051f320/1 6 rev. 1.4 16.5.3.slave receiver mode ....... ............................................................. ......... 182 16.5.4.slave transmitter mode .... ............... ............................................. ......... 183 16.6.smbus status decoding ........................................................................ ......... 184 17. uart0................ ........................................................................................... ......... 187 17.1.enhanced baud rate g eneration.................. ................................................. 188 17.2.operational modes ....... ......................................................................... ......... 188 17.2.1.8-bit uart ........... ......................................................................... ......... 189 17.2.2.9-bit uart ........... ......................................................................... ......... 190 17.3.multiprocessor communications ... ........................................................ ......... 190 18. enhanced serial peripheral interface (spi0)..... ................................................. 195 18.1.signal descriptions....... ......................................................................... ......... 196 18.1.1.master out, slave in (mos i)...................... ................................. ........... 196 18.1.2.master in, slave out (miso)............... .......................................... ......... 196 18.1.3.serial clock (sck) ........... ............................................................. ......... 196 18.1.4.slave select (nss) .......... ............................................................. ......... 196 18.2.spi0 master mode operation . ............................................................... ......... 197 18.3.spi0 slave mode operation ..... ............................................................. ......... 198 18.4.spi0 interrupt sources ........ .................................................................. ......... 199 18.5.serial clock timing... ............................................................................. ......... 199 18.6.spi special function registers . ............... ............................................. ......... 202 19. timers ................... .................................................................................. .............. 20 9 19.1.timer 0 and ti mer 1 ............... ............................................................... ......... 209 19.1.1.mode 0: 13-bit counter/timer ................. .............. ............... .................. 209 19.1.2.mode 1: 16-bit counter/timer ................. .............. ............... .................. 211 19.1.3.mode 2: 8-bit counter/tim er with auto-reload.......... ................. ........... 211 19.1.4.mode 3: two 8-bit counter /timers (timer 0 only)..... ................. ........... 212 19.2.timer 2 ............. .................................................................................. ........... 217 19.2.1.16-bit timer with auto-rel oad............... ................................................. 217 19.2.2.8-bit timers with auto-rel oad............... ................................................. 218 19.2.3.usb start-of-frame captur e.................................................................. 219 19.3.timer 3 ............. .................................................................................. ........... 222 19.3.1.16-bit timer with auto-rel oad............... ................................................. 222 19.3.2.8-bit timers with auto-rel oad............... ................................................. 223 19.3.3.usb start-of-frame captur e.................................................................. 224 20. programmable counter array (pca 0) ............... ................................................. 227 20.1.pca counter/timer ............. .................................................................. ......... 228 20.2.capture/compare modules ...... ............................................................. ......... 229 20.2.1.edge-triggered captur e mode................. .............. ............... .................. 230 20.2.2.software timer (compare) mode................. ................................. ......... 232 20.2.3.high speed output mode.............................................................. ......... 233 20.2.4.frequency output mode ....... ........................................................ ......... 234 20.2.5.8-bit pulse width modulato r mode............... ................................. ......... 235 20.2.6.16-bit pulse width modulat or mode............. ................................. ......... 236 20.3.watchdog timer mode .... ...................................................................... ......... 236 20.3.1.watchdog timer operation ... ........................................................ ......... 237
rev. 1.4 7 c8051f320/1 20.3.2.watchdog timer usage ........ ........................................................ ......... 238 20.4.register descriptions for pca. ............... ............................................... ......... 239 21. c2 interface ................ .................................................................................. ......... 245 21.1.c2 interface registers......... .................................................................. ......... 245 21.2.c2 pin sharing ......... ............................................................................. ......... 247
c8051f320/1 8 rev. 1.4 list of figures and tables 1. system overview table 1.1. product selection guide . ............... ............................................. ........... 16 figure 1.1. c8051f320 block diagr am ...................... ................................. ............. 16 figure 1.2. c8051f321 block diagr am ...................... ................................. ............. 17 figure 1.3. on-chip clock and rese t ........................................................... ........... 19 figure 1.4. on-board memory ma p.................. ............................................. ........... 20 figure 1.5. usb controll er block diagram.......... .......................................... ........... 21 figure 1.6. development/in-syst em debug diagram................. ................. ............. 22 figure 1.7. digital cro ssbar diagram ............... ............................................. ........... 23 figure 1.8. pca block diagram ..... ............................................................... ........... 24 figure 1.9. pca block diagram ..... ............................................................... ........... 24 figure 1.10. 10-bit adc block diagram ....... ................................................. ........... 25 figure 1.11. compar ator0 block diagram ........ ............................................. ........... 26 2. absolute maximum ratings table 2.1. absolute maximum rati ngs ................... .............. ............... ........... ......... 27 3. global electrical characteristics table 3.1. global electrical char acteristics ............ .............. ............... ........... ......... 28 table 3.2. index to electrical characteristics tables ................................. ............. 29 4. pinout and package definitions table 4.1. pin definitions for the c8051f320/1 .......... ................................. ........... 30 figure 4.1. lqfp-32 pi nout diagram (top view) ............... ............................ ......... 32 figure 4.2. qfn-28 pinout diagr am (top view) .......... ................................. ........... 36 5. 10-bit adc (adc0) figure 5.1. adc0 functional bl ock diagram.............. ................................. ............. 39 figure 5.2. temperature sensor transfer function ..... ................................. ........... 41 figure 5.3. temperature sens or error with 1-point calib ration (vref = 2.40 v).... 42 figure 5.4. 10-bit adc track and conversion example timing ................. ............. 44 figure 5.5. adc0 equiva lent input circuits. ............... ................................. ............. 45 figure 5.6. adc window compare example: right-jus tified single-ended data ... 52 figure 5.7. adc window co mpare example: left-justifi ed single-ended data ..... 52 figure 5.8. adc window co mpare example: right-justifi ed differential data ....... 53 figure 5.9. adc window com pare example: left-justified di fferential data.......... 53 table 5.1. adc0 elec trical characteristics ................. ................................. ........... 54 6. voltage reference figure 6.1. voltage reference functional block diagram ....... ............ ........... ......... 55 table 6.1. voltage reference elec trical characteristi cs .............. ................ ........... 56 7. comparators figure 7.1. comparator0 functi onal block diagram .... ................................. ........... 57 figure 7.2. comparator1 functi onal block diagram .... ................................. ........... 58 figure 7.3. comparator hysteres is plot ........... ............................................. ........... 59 table 7.1. comparator electrical characteristics ... .............. ............... ........... ......... 66 8. voltage regulator (reg0)
rev. 1.4 9 c8051f320/1 figure 8.1. external capacitors for voltage regulator input/output . .............. ......... 67 table 8.1. voltage regula tor electrical s pecifications ................. ................ ........... 68 figure 8.2. reg0 configuratio n: usb bus-powered ... ................................. ........... 68 figure 8.3. reg0 configuratio n: usb self-powered ............ ............... ........... ......... 69 figure 8.4. reg0 configurat ion: usb self-powered, regulat or disabled .............. 69 figure 8.5. reg0 configuratio n: no usb connection.. ................................ ........... 70 9. cip-51 microcontroller figure 9.1. cip-51 block diagram.. ............................................................... ........... 71 table 9.1. cip-51 instruction se t summary.............. ................................. ............. 73 figure 9.2. memory map ........... .................................................................. ............. 77 table 9.2. special function re gister (sfr) memory map...... ............ ........... ......... 79 table 9.3. special functi on registers ............... .......................................... ........... 80 table 9.4. interrupt summ ary .................. .................................................. ............. 89 10. reset sources figure 10.1. rese t sources.............. ............................................................. ........... 99 figure 10.2. power-on and vdd monitor reset timing ....... ............... .................. 100 table 10.1. reset electrical char acteristics ........... .............. ............... .................. 105 11. flash memory table 11.1. flash electric al characteristics ....... .......................................... ......... 107 figure 11.1. flash program me mory map and security byte... ............ .................. 108 table 11.2. flash security summar y ............................................................ ......... 109 12. external ram figure 12.1. external ram memory map............. .......................................... ......... 114 figure 12.2. xram memory map expanded view ......... ............................... ......... 115 13. oscillators figure 13.1. oscillator diagram............... ............................................................... 116 table 13.1. typical usb full speed clock settings..... ................................. ......... 123 table 13.2. typical usb low spee d clock settings.... ................................. ......... 124 table 13.3. internal oscillator el ectrical characteristics ...... ............... .................. 125 14. port input/output figure 14.1. port i/o functional block diagram ................ ............................ ......... 126 figure 14.2. port i/o ce ll block diagram ............ .......................................... ......... 127 figure 14.3. crossbar priority decoder with no pins sk ipped ............... ................ 128 figure 14.4. crossbar priority decoder with crystal pins skipped .......... .............. 129 table 14.1. port i/o dc electrical characteristics ........... ............................ ......... 138 15. universal serial bus controller (usb) figure 15.1. usb0 block diagram................ ................................................. ......... 139 table 15.1. endpoint addr essing scheme .............. .............. ............... .................. 140 figure 15.2. usb0 regi ster access scheme........ ................................................. 142 table 15.2. usb0 c ontroller registers .......... ............................................... ......... 144 figure 15.3. usb fifo al location ............. .................................................. ........... 147 table 15.3. fifo configur ations ............... .................................................. ........... 148 table 15.4. usb transceiver elec trical characteristics .......... ............ .................. 168 16. smbus figure 16.1. smbus block diagram ............. ................................................. ......... 169
c8051f320/1 10 rev. 1.4 figure 16.2. typical smbu s configuration .......... .......................................... ......... 170 figure 16.3. smbus transac tion ............. ............................................................... 171 table 16.1. smbus clock source selection................................................ ........... 173 figure 16.4. typical sm bus scl generation........ ................................................. 174 table 16.2. minimum sda setup and hold times ....... ................................. ......... 174 table 16.3. sources for hardwa re changes to smb0cn .......... ................. ........... 178 figure 16.5. typical ma ster transmitter sequence............. ................................... 180 figure 16.6. typical ma ster receiver sequence................. ................................... 181 figure 16.7. typical slave rece iver sequence............ ................................. ......... 182 figure 16.8. typical slave trans mitter sequence........ ................................. ......... 183 table 16.4. smbus status decoding. ............... ............................................. ......... 184 17. uart0 figure 17.1. uart0 block diagram ............. ................................................. ......... 187 figure 17.2. uart0 baud rate logic ............ ............................................... ......... 188 figure 17.3. uart interconnect di agram ............. ................................................. 189 figure 17.4. 8-bit uart timing diagram............ .......................................... ......... 189 figure 17.5. 9-bit uart timing diagram............ .......................................... ......... 190 figure 17.6. uart multi-proc essor mode interconne ct diagram .......... ................ 191 table 17.1. timer settings for standard baud rates using the internal oscillator .... 194 18. enhanced serial peripheral interface (spi0) figure 18.1. spi bl ock diagram ............ ........................................................ ......... 195 figure 18.2. multiple -master mode connection diagram ...... ............... .................. 198 figure 18.3. 3-wire single master and sl ave mode connection di agram ............. 198 figure 18.4. 4-wire single master mode and 4-wire slave m ode connection diagram 198 figure 18.5. master mode data/ clock timing .............. ................................. ......... 200 figure 18.6. slave mode data/clock timing (ckpha = 0) ... ............... .................. 200 figure 18.7. slave mode data/clock timing (ckpha = 1) ... ............... .................. 201 figure 18.8. spi ma ster timing (ckpha = 0).. ............................................. ......... 206 figure 18.9. spi ma ster timing (ckpha = 1).. ............................................. ......... 206 figure 18.10. spi slave timing (c kpha = 0).............. ................................. ......... 207 figure 18.11. spi slave timing (c kpha = 1).............. ................................. ......... 207 table 18.1. spi slave timing para meters ............ ................................................. 208 19. timers figure 19.1. t0 mode 0 bl ock diagram............... .......................................... ......... 210 figure 19.2. t0 mode 2 bl ock diagram............... .......................................... ......... 211 figure 19.3. t0 mode 3 bl ock diagram............... .......................................... ......... 212 figure 19.4. timer 2 16- bit mode block diagram .. ................................................ 217 figure 19.5. timer 2 8- bit mode block diagram .. ................. ............... .................. 218 figure 19.6. timer 2 so f capture mode (t2split = ?0?)................. ..................... 219 figure 19.7. timer 2 so f capture mode (t2split = ?1?)................. ..................... 219 figure 19.8. timer 3 16- bit mode block diagram .. ................................................ 222 figure 19.9. timer 3 8- bit mode block diagram .. ................. ............... .................. 223 figure 19.10. timer 3 sof capt ure mode (t3split = ?0?)...... ............ .................. 224
rev. 1.4 11 c8051f320/1 figure 19.11. timer 3 sof capt ure mode (t3split = ?1?)...... ............ .................. 224 20. programmable counter array (pca0) figure 20.1. pca block diagram.... ............................................................... ......... 227 table 20.1. pca timebase input op tions ............. ................................................. 228 figure 20.2. pca counter /timer block diagram.... ................................................ 228 table 20.2. pca0cpm regist er settings for pca capt ure/compare modules ..... 229 figure 20.3. pca interrupt blo ck diagram ................. ................................. ........... 230 figure 20.4. pca captur e mode diagram............. ................................................. 231 figure 20.5. pca software time r mode diagram ........ ................................. ......... 232 figure 20.6. pca high speed output mode diagram........... ............... .................. 233 figure 20.7. pca fr equency output mode ......... .......................................... ......... 234 figure 20.8. pca 8-bit pwm mode diagram .......... .............. ............... .................. 235 figure 20.9. pca 16-bit pwm mode ............................................................. ......... 236 figure 20.10. pca module 4 with watchdog ti mer enabled ..... ................. ........... 237 table 20.3. watchdog time r timeout intervals 1 ................................................................... 239 21. c2 interface figure 21.1. typical c2 pin sharing.......... .................................................. ........... 247
c8051f320/1 12 rev. 1.4 list of registers sfr definition 5.1. amx0p: amux 0 positive channel select . . . . . . . . . . . . . . . . . . 46 sfr definition 5.2. amx0n: amux 0 negative channel select . . . . . . . . . . . . . . . . . . 47 sfr definition 5.3. adc0cf: adc0 c onfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sfr definition 5.4. adc0h: adc0 data word msb . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sfr definition 5.5. adc0l: adc0 data word lsb . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 sfr definition 5.6. adc0cn: adc0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 sfr definition 5.7. adc0gth: a dc0 greater-than data high byte . . . . . . . . . . . . . 50 sfr definition 5.8. adc0gtl: adc0 greater-than data low byte . . . . . . . . . . . . . 50 sfr definition 5.9. adc0lth: ad c0 less-than data high byte . . . . . . . . . . . . . . . . 51 sfr definition 5.10. adc0ltl: adc0 less-than data low byte . . . . . . . . . . . . . . . 51 sfr definition 6.1. ref0cn: reference control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 sfr definition 7.1. cpt0cn : comparator0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 sfr definition 7.2. cpt0mx : comparator0 mux select ion . . . . . . . . . . . . . . . . . . . . 61 sfr definition 7.3. cpt0md : comparator0 mode selection . . . . . . . . . . . . . . . . . . . . 62 sfr definition 7.4. cpt1cn : comparator1 control . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 sfr definition 7.5. cpt1mx : comparator1 mux select ion . . . . . . . . . . . . . . . . . . . . 64 sfr definition 7.6. cpt1md : comparator1 mode selection . . . . . . . . . . . . . . . . . . . . 65 sfr definition 8.1. reg0cn : voltage regulator control . . . . . . . . . . . . . . . . . . . . . . 70 sfr definition 9.1. dpl: da ta pointer low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 sfr definition 9.2. dph: data pointer high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 sfr definition 9.3. sp: stack pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 sfr definition 9.4. psw: program st atus word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 sfr definition 9.5. acc: accu mulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sfr definition 9.6. b: b register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 sfr definition 9.7. ie: interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 sfr definition 9.8. ip: interr upt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 sfr definition 9.9. eie1: extended interrupt enable 1 . . . . . . . . . . . . . . . . . . . . . . . . 93 sfr definition 9.10. eip1: extended inte rrupt priority 1 . . . . . . . . . . . . . . . . . . . . . . . 94 sfr definition 9.11. eie2: extended interrupt enable 2 . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 9.12. eip2: extended inte rrupt priority 2 . . . . . . . . . . . . . . . . . . . . . . . 95 sfr definition 9.13. it01cf: int0/int 1 configuration . . . . . . . . . . . . . . . . . . . . . . . . 96 sfr definition 9.14. pc on: power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 sfr definition 10.1. vdm0cn : vdd monitor control . . . . . . . . . . . . . . . . . . . . . . . . 101 sfr definition 10.2. rstsrc: reset source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 sfr definition 11.1. psctl: program store r/w control . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 11.2. flkey: flash lock and key . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 sfr definition 11.3. flscl: flash scale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 sfr definition 12.1. emi0cn: external memory interface control . . . . . . . . . . . . . . 115 sfr definition 13.1. oscicn: inter nal oscillator control . . . . . . . . . . . . . . . . . . . . . 118 sfr definition 13.2. oscicl: intern al oscillator calibration . . . . . . . . . . . . . . . . . . . 118 sfr definition 13.3. oscxcn: external oscillator c ontrol . . . . . . . . . . . . . . . . . . . . 121 sfr definition 13.4. clkmul : clock multiplier control . . . . . . . . . . . . . . . . . . . . . . . 122 sfr definition 13.5. clksel: clock select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
rev. 1.4 13 c8051f320/1 sfr definition 14.1. xbr0: port i/o crossbar regist er 0 . . . . . . . . . . . . . . . . . . . . . 131 sfr definition 14.2. xbr1: port i/o crossbar regist er 1 . . . . . . . . . . . . . . . . . . . . . 132 sfr definition 14.3. p0: port 0 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 sfr definition 14.4. p0mdin : port0 input mode regist er . . . . . . . . . . . . . . . . . . . . . 133 sfr definition 14.5. p0md out: port0 output mode register . . . . . . . . . . . . . . . . . 133 sfr definition 14.6. p0 skip: port0 skip register . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 14.7. p1: port 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 14.8. p1mdin : port1 input mode regist er . . . . . . . . . . . . . . . . . . . . . 134 sfr definition 14.9. p1md out: port1 output mode register . . . . . . . . . . . . . . . . . 135 sfr definition 14.10. p1skip: port1 skip register . . . . . . . . . . . . . . . . . . . . . . . . . . 135 sfr definition 14.11. p2: port 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 sfr definition 14.12. p2mdin: port 2 input mode register . . . . . . . . . . . . . . . . . . . . 136 sfr definition 14.13. p2md out: port2 output mode register . . . . . . . . . . . . . . . . 136 sfr definition 14.14. p2skip: port2 skip register . . . . . . . . . . . . . . . . . . . . . . . . . . 136 sfr definition 14.15. p3: port 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 sfr definition 14.16. p3mdin: port 3 input mode register . . . . . . . . . . . . . . . . . . . . 137 sfr definition 14.17. p3md out: port3 output mode register . . . . . . . . . . . . . . . . 137 sfr definition 15.1. usb0x cn: usb0 transceiver control . . . . . . . . . . . . . . . . . . . 141 sfr definition 15.2. usb0a dr: usb0 indirect addre ss . . . . . . . . . . . . . . . . . . . . . . 143 sfr definition 15.3. usb0dat: usb0 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 usb register definition 15. 4. index: usb0 endpoint index . . . . . . . . . . . . . . . . . . . 145 usb register definition 15.5. clkrec: clock reco very control . . . . . . . . . . . . . . . 146 usb register definition 15.6. fifon: usb0 endpoint fifo a ccess . . . . . . . . . . . . . 148 usb register definition 15.7. faddr: usb0 function address . . . . . . . . . . . . . . . . 149 usb register definition 15. 8. power: usb0 power . . . . . . . . . . . . . . . . . . . . . . . . 151 usb register definition 15.9. framel: usb0 frame number low . . . . . . . . . . . . . 152 usb register definiti on 15.10. frameh: usb0 frame number high . . . . . . . . . . . 152 usb register definition 15.11. in1int: usb0 in endpoint interrupt . . . . . . . . . . . . 153 usb register definition 15.12. out1int: usb0 ou t end point interrupt . . . . . . . . . . 154 usb register definition 15.13. cmint: usb0 common interrupt . . . . . . . . . . . . . . . 155 usb register definition 15.14. in1ie: usb0 in endpoint interrupt enab le . . . . . . . . 156 usb register definiti on 15.15. out1ie: usb0 out endpoint interrupt enable . . . . . 156 usb register definition 15.16. cmie: usb0 comm on interrupt enable . . . . . . . . . . 157 usb register definition 15.17. e0csr: usb0 endpoi nt0 control . . . . . . . . . . . . . . . 160 usb register definition 15.18. e0cnt: usb0 endpoint 0 data count . . . . . . . . . . . 161 usb register definiti on 15.19. eincsrl: usb0 in endpoi nt control low byte . . . . 163 usb register definiti on 15.20. eincsrh: usb0 in endpoi nt control high byte . . . 164 usb register definiti on 15.21. eoutcsrl: usb0 out endpoint contro l high byte . . 166 usb register definiti on 15.22. eoutcsrh: us b0 out endpoint cont rol low byte . . 167 usb register definiti on 15.23. eoutcntl: usb0 out e ndpoint count low . . . . . 167 usb register defini tion 15.24. eoutcnth: usb0 out endpoint count high . . . . 167 sfr definition 16.1. smb0cf: smbus clock/configuration . . . . . . . . . . . . . . . . . . . 175 sfr definition 16.2. smb0cn : smbus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
c8051f320/1 14 rev. 1.4 sfr definition 16.3. smb0dat: smbus data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 sfr definition 17.1. scon0: serial port 0 control . . . . . . . . . . . . . . . . . . . . . . . . . . 192 sfr definition 17.2. sbuf0: serial (uart0) port data buffer . . . . . . . . . . . . . . . . . 193 sfr definition 18.1. spi0cfg: spi0 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 203 sfr definition 18.2. spi0cn: spi0 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 sfr definition 18.3. spi0ck r: spi0 clock rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 sfr definition 18.4. spi0dat: spi0 data register . . . . . . . . . . . . . . . . . . . . . . . . . . 205 sfr definition 19.1. tcon: timer cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 sfr definition 19.2. tmod: ti mer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 sfr definition 19.3. ckcon: clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 sfr definition 19.4. tl0: timer 0 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 sfr definition 19.5. tl1: timer 1 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 sfr definition 19.6. th0: timer 0 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 sfr definition 19.7. th1: timer 1 hi gh byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 sfr definition 19.8. tmr2cn: timer 2 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 sfr definition 19.9. tmr2rll: ti mer 2 reload register low byte . . . . . . . . . . . . . 221 sfr definition 19.10. tmr2 rlh: timer 2 reload re gister high byte . . . . . . . . . . . 221 sfr definition 19.11. tmr2l: timer 2 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 sfr definition 19.12. tmr2h timer 2 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 sfr definition 19.13. tmr3cn: timer 3 control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 sfr definition 19.14. tmr3 rll: timer 3 reload regi ster low byte . . . . . . . . . . . . 226 sfr definition 19.15. tmr3 rlh: timer 3 reload re gister high byte . . . . . . . . . . . 226 sfr definition 19.16. tmr3l: timer 3 low byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 sfr definition 19.17. tmr3h timer 3 high byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 sfr definition 20.1. pca0cn: pca control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 sfr definition 20.2. pca0md: pca mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 sfr definition 20.3. pc a0cpmn: pca capture/compare mode . . . . . . . . . . . . . . . 242 sfr definition 20.4. pca0l: pca counter/timer low byte . . . . . . . . . . . . . . . . . . . 243 sfr definition 20.5. pca0h: pca coun ter/timer high byte . . . . . . . . . . . . . . . . . . 243 sfr definition 20.6. pca0cpln: pca capture module low byte . . . . . . . . . . . . . . . 243 sfr definition 20.7. pca0cphn: pca capture module high byte . . . . . . . . . . . . . . 244 c2 register definition 21.1. c2add: c2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 c2 register definition 21.2. c2 device id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 c2 register definition 21.3. revid: c2 revision id . . . . . . . . . . . . . . . . . . . . . . . . . 246 c2 register definition 21.4. fp ctl: c2 flash programming cont rol . . . . . . . . . . . . 246 c2 register definition 21.5. fp dat: c2 flash programming data . . . . . . . . . . . . . . 246
rev. 1.4 15 c8051f320/1 1. system overview c8051f320/1 devices are fully integrated mixed-signal system-on-a-chip mcus. highlighted features are listed below. refer to ta b l e 1.1 for specific product feature selection. ? high-speed pipelined 8051-compatible microcontroller core (up to 25 mips) ? in-system, full-speed, non-intrusive debug interface (on-chip) ? universal serial bus (usb) function controller wit h eigh t flexible endpoint pipes, integrated trans - ceiver, and 1k fifo ram ? supply voltage regulator (5-to-3 v) ? true 10-bit 200 ksps 17-channel single-ended/diffe rential ad c with analog multiplexer ? on-chip voltage reference and temperature sensor ? on-chip voltage comparators (2) ? precision programmable 12 mhz internal oscillator and 4x clock multiplier ? 16 kb of on-chip flash memory ? 2304 total bytes of on-chip ram (256 + 1k + 1k usb fifo) ?smbus/i 2 c, enhanced uart, and enhanced spi seri al interfaces implemented in hardware ? four general-purpose 16-bit timers ? programmable counter/timer array (pca) with five capture/compare modules and watchdog timer func tion ? on-chip power-on reset, vdd monitor, and missing clock detector ? 25/21 port i/o (5 v tolerant) with on-chip power-on rese t, vdd monitor, voltage regulator, wa tchdog timer, and clock oscillator, c8051f320/1 devices are truly stand-alone system-on-a-chip solutions. the flash memory can be repro - grammed in-circuit, providin g no n-volatile data storage, and also allowing field upgrades of the 8051 firm - ware. user software has co mplete control of all peripherals and may individually sh ut down any or all peripherals for power savings. the on-chip silicon labs 2- wire (c2) d evelopment interface allo ws non-intrusive (uses no on-chip resources), full speed, in-circuit debugging using the production mcu installed in the final application. this debug logic supports inspection and modification of memory and registers, setting breakpoints, single stepping, run and halt commands. all analog and digita l peripherals are fully functional while debugging using c2. the two c2 interface pins can be shared with user functions , allowing in-system debugging with - out occupying package pins. each device is specified for 2.7-to-3.6 v operation over the industrial temperature range (?40 to +85 c). ( note that 3.0-to-3.6 v is required for usb communication.) the po rt i/o and /rst pins are tolerant of input signals up to 5 v. c8051f320/1 are available in a 32-pin lqfp or a 28-pin qfn package.
table 1.1. product selection guide mips (peak) flash memory ram calibrated internal oscillator usb supply voltage regulator smbus/i 2 c enhanced spi uart timers (16-bit) programmable counter array digital port i/os 10-bit 200ksps adc temperature sensor voltage reference analog comparators package (lead-free, rohs-compliant) uart 16kbyte flash 256 byte sram por sfr bus 8 0 5 1 c o r e reset /rst/c2ck external oscillator circuit debug hw brown- out p 0 d r v 1k byte xram xtal1 xtal2 p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4 p0.5 p0.6/cnvstr p0.7/vref spi regin c r o s s b a r p 1 d r v p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 port 0 latch smbus timer 0,1,2,3 / rtc port 1 latch system clock p 2 d r v p 3 d r v p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 p3.0/c2d 10-bit 200ksps adc a m u x ain0-ain16 vref vdd cp1 + - temp vdd cp0 + - c2d port 2 latch port 3 latch pca/ wdt usb controller usb transceiver analog/digital power voltage regulator 5.0v 1k byte usb sram vbus d+ d- vref 12mhz internal oscillator gnd vdd in out enable vref x4 2 usb clock 2 1,2,3,4 clock recovery c8051f320/1 16 rev. 1.4 figure 1.1. c8051f320 block diagram c8051f320-gq 25 16 k 2304 ?????? 4 ? 25 ??? 2lqfp-32 c8051f321-gm 25 16 k 2304 ?????? 4 ? 21 ??? 2qfn-28
uart 16kbyte flash 256 byte sram por sfr bus 8 0 5 1 c o r e reset /rst/c2ck external oscillator circuit debug hw brown- out p 0 d r v 1k byte xram xtal1 xtal2 p0.0 p0.1 p0.2/xtal1 p0.3/xtal2 p0.4 p0.5 p0.6/cnvstr p0.7/vref spi regin c r o s s b a r p 1 d r v p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 port 0 latch smbus timer 0,1,2,3 / rtc port 1 latch system clock p 2 d r v p 3 d r v p2.0 p2.1 p2.2 p2.3 p3.0/c2d 10-bit 200ksps adc a m u x ain0-ain11 vref vdd cp1 + - temp vdd cp0 + - c2d port 2 latch port 3 latch pca/ wdt usb controller usb transceiver analog/digital power voltage regulator 5.0v 1k byte usb sram vbus d+ d- vref 12mhz internal oscillator gnd vdd in out enable vref x4 2 usb clock 2 1,2,3,4 clock recovery rev. 1.4 17 c8051f320/1 figure 1.2. c8051f321 block diagram
c8051f320/1 18 rev. 1.4 1.1. cip-51? microcontroller core 1.1.1. fully 8051 compatible the c8051f320/1 family utilizes silicon labs' proprietary cip-51 microcon troller core. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemblers and compilers can be used to develop software. the cip-51 core offers all th e peripherals included with a standard 8052, including four 16-bit counter/timers, a full- duplex uart with extended baud rate configuration, an enhanced spi port, 2304 bytes of on-chip ram, 128 byte special function register (sfr) address space, and 25/21 i/o pin s. 1.1.2. improved throughput the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute with a ma ximum system clock of 12-to-24 mhz. by contrast, the cip-51 core exe - cutes 70% of its instructions in one or two system clock cy cles, with only four inst ructions taking more than four system clock cycles. the cip-51 has a total of 109 instructions. the table be low shows the total number of instructions that require each execution time. 1.1.3. additional features the c8051f320/1 soc family includes several key enhancements to the cip-51 core and peripherals to improve performance and ease of use in end applications. the extended interrupt handler provides 16 interrupt sources into the cip-51 (as opposed to 7 for the stan - dard 8051), allowing numerous analog and digital peripherals to interrupt the controller. an interrupt driven sys tem requires less interv ention by the mcu, giving it more effe ctive throughput. the extra interrupt sources are very useful when build ing multi-tasking, real-time systems. nine reset sources are available: power-on reset circuitry (por), an on-chip vdd monitor (forces reset whe n power supply voltage drops below v rst as given in ta b l e 10.1 on page 105 ), the usb controller (usb bus reset or a vbus transition), a watchdog time r , a missing clock detector, a voltage level detec - tion from comparator0, a forced software reset, an external reset pin, and an errant flash read/write pro - tection circuit. each reset source e xcept for the por, reset input pin, or flash error may be disabled by the user in software. the wdt may be permanently enabled in software after a power-on reset during mcu initialization. the internal oscillator is factory calibrated to 12 mhz 1.5%, and the internal oscillator period may be user programmed in ~0.25% increments. a clock recovery mechanism allo ws the internal oscillator to be used with the 4x clock multiplier as the usb clock source in full speed mode; th e internal oscillator can also be used as the usb clock source in low speed mode. external oscillators may also be used with the 4x clock multiplier. an external oscillator drive circuit is also included, allowing an exte rnal crystal, ceramic resona - tor, capacitor, rc, or cmos clock source to genera t e the system clock. the system clock may be config - ured to use the internal oscillator, ex ternal oscillator , or the clock multiplie r output divided by 2. if desired, the system clock source may be switched on-the-fly be tween oscillator sources. an external oscillator can be extremely useful in low power applications, allowing the mcu to run from a slow (power saving) exter - nal clock source, while periodically switch ing to the internal os cillator as needed. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1
rev. 1.4 19 c8051f320/1 figure 1.3. on-chi p clock and reset 1.2. on-chip memory the cip-51 has a standard 8051 program and data addr ess configuration. it in cludes 256 bytes of data ram, with the upper 128 bytes dual-mapped. indirect addressing accesses the upper 128 bytes of general purpose ram, and direct addressing accesses the 128 byte sfr addre ss space. the lower 128 bytes of ram are accessible via direct and indirect addressing. the first 32 bytes are addressable as four banks of general purpose registers, and the next 16 byte s can be byte addressable or bit addressable. program memory consists of 16 kb of flash. this me mory may be reprogrammed in-system in 512 byte sectors, and requires no special off-chip programming voltage. see figure 1.4 for the mcu system mem - ory map. pca wdt missing clock detector (one- shot) software reset (swrsf) system reset reset funnel px.x px.x en system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable errant flash operation + - comparator 0 c0rsef /rst (wired-or) power on reset + - vdd supply monitor enable '0' internal oscillator xtal1 xtal2 external oscillator drive clock multiplier usb controller vbus transition enable
c8051f320/1 20 rev. 1.4 figure 1.4. on-board memory map 1.3. universal serial bus controller the universal serial bus controller (usb0) is a usb 2.0 compliant full or low speed function with inte - grated transceiver and endpoint fifo ram. a total of e ight endpoint pipes are available: a bi-directional control endpoint (endpoint0) and three pairs of in/out endpoints (endpoints1-3 in/out). a 1k block of xram is used as dedicated usb fi fo sp ace. this fifo sp ace is distributed among endpoints0?3; endpoint1?3 fifo slots can be configured as in, out, or both in and out (split mode). the maximum fifo size is 512 bytes (endpoint3). usb0 can be operated as a full or low speed function. on-chip 4x clock multiplier and clock recovery cir - cuitry allow both full and low speed options to be implemented with the on-chip precision oscillator as the usb clock source. an ex ternal oscillator source can also be used with the 4x clock multiplier to generate the usb clock. the cpu clock source is independent of the usb clock. same 2048 bytes as from 0x0000 to 0x07ff, wrapped on 2 kb boundaries program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 1024 bytes (accessable using movx instruction) 0x0000 0x03ff 0x0400 0xffff 16 k flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x3e00 0x3dff 0x07ff 0x0800 usb fifos 1024 bytes
rev. 1.4 21 c8051f320/1 the usb transceiver is usb 2.0 compliant, and includes on-chip matching and pull-up resistors. the pull- up resistors can be enabled/disabled in software , and will appear on the d+ or d? pin according to the soft - ware-selected speed setting (full or low speed). figure 1.5. usb contro ller block diagram 1.4. voltage regulator c8051f320/1 devices include a 5-to-3 v voltage regulator (reg0). when enabled, the reg0 output a ppears on the vdd pin and can be used to power ex ternal devices. reg0 can be enabled/disabled by software. 1.5. on-chip debug circuitry the c8051f320/1 devices include on-chip silicon labs 2-wire (c2) debug circuitry that provides non-intru - sive, full speed, in-circuit debugging of the production part inst alled in the end application. silicon labs' debugging syst em support s inspection and modificati on of memory and registers, break - points, and single stepping. no additional target ram, pr ogram memory, timers, or communications chan - nels are required. all the digital and analog periphera ls are functional and work correctly while debugging. all the peripherals (except for the usb, adc, and smbus) are stalled when the mcu is halted, during sin - gle stepping, or at a breakpoint in order to keep them synchronized. the c8051f320dk development kit provides all the har dwar e and software necessary to develop applica - tion code and perform in-circuit debugging with the c8 051f320/1 mcus. the kit includes software with a developer's studio and debugger, 8051 assembler and linker, evalua tion ?c? compiler, and a debug adapter. it also has a target application board with the c8051f320 mcu installed, the necessary cables for connection to a pc, and a wall-mount power supply. the development kit contents may also be used to program and debug the device on the production pcb using the appropriate connections for the program - ming pins. the silicon labs ide interface is a vastl y superior developing and debu gging configuratio n, compared to standard mcu emulators that use on-board "ice chips" and require the mcu in the application board to transceiver serial interface engine (sie) usb fifos (1k ram) d+ d- vdd endpoint0 in/out endpoint1 in out endpoint2 in out endpoint3 in out data transfer control cip-51 core usb control, status, and interrupt registers
c8051f320/1 22 rev. 1.4 be socketed. silicon labs' debug para digm increases ease of use and preserves the performance of the precision analog peripherals. figure 1.6. development/in -system debug diagram 1.6. programmable digital i/o and crossbar c8051f320 devices include 25 i/o pins (three byte -wide ports and one 1-bit-wide port); c8051f321 devices include 21 i/o pins (two byte-wide ports, one 4-bit-wide port, and one 1-bit-wide port). the c8051f320/1 ports behave like typical 8051 ports with a few enhancements. each port pin may be config - ured as an analog input or a digital i/o pin. pins sele cted as dig ital i/os may additionally be configured for push-pull or open-drain output. the ?weak pull-ups? th at are fixed on typical 8051 devices may be globally disabled, providing powe r savings capabilities. the digital crossbar allows mappin g of internal digital system resources to port i/o pins (see figure 1.7 ). on-chip counter/timers, serial buses, hw interrupts, co mparator outputs, and other digital signals in the controller can be configured to appear on the port i/o pins specified in the crossbar control registers. this allows the user to select the exact mix of general purpose port i/o and digital resources needed for the particular application. pc usb cable usb debug adapter ac/dc adapter target board silicon laboratories pwr p1.6 p3.7 reset port 4 port 3 port 1 port 2 port 0 mcu silicon laboratories usb debug adapter run stop power
rev. 1.4 23 c8051f320/1 figure 1.7. digital crossbar diagram 1.7. serial ports the c8051f320/1 family includes an smbus/i 2 c interface, a full-duplex uart with enhanced baud rate configuration, and an enhanced spi interface. each of the serial buses is fully implemented in hardware and makes extensive use of the cip-51's interrup ts, thus requiring very little cpu intervention. 1.8. programmable counter array an on-chip programmable counter/timer array (pca) is included in addition to the four 16-bit general pur - pose counter/timers. the pca consists of a dedicated 16-bit counter/timer time base with five programma - ble capture/compare modules. the pca clock is derived fr om one of six sources: the system clock divided by 12, the system clock divided by 4, timer 0 overflow s, an external clock input (eci), the system clock, or the external oscillator clock source di vided by 8. the ex ternal clock source selecti on is useful for real-time clock functionality, where the pca is clocked by an ex ternal source while the internal oscillator drives the system clock. each capture/compare module can be configured to operate in one of six modes: edge-triggered capture, sof tware timer, high speed output, 8- or 16-bit pulse width modulator, or frequency output. additionally, capture/compare module 4 offers watchdog timer (wdt) capabilit ies. following a system reset, module 4 is configured and enabled in wdt mode. the pca capture/compare module i/o and external clock input may be routed to port i/o via the digital crossbar. xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 pnmdout, pnmdin registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 6 pca cp1 outputs 2 4 spi cp0 outputs 2 p1 i/o cells p1.0 p1.7 8 p2 i/o cells p2.0 p2.7 8 p3 i/o cells p3.0 1 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) (p2.0-p2.7) (p3.0) 8 8 8 8 p1 p2 p3 note: p2.4-p2.7 only available on the c8051f320
c8051f320/1 24 rev. 1.4 figure 1.9. pc a block diagram 1.9. 10-bit analog to digital converter the c8051f320/1 devices include an on-chip 10-bit sar adc with a 17-channel differential input multi - plexer. with a maximum throughput of 200 ksps, the adc offers true 10-bit linearity with an inl of 1lsb. th e adc system includes a configurable analog multiplexer that selects both positive and negative adc inputs. ports1-3 are available as adc inputs; additio nally, the on-chip temperature sensor output and the power supply voltage (vdd) are available as adc inpu ts. user firmware may shut down the adc to save power. conversions can be started in six ways: a software comma nd, a n overflow of timer 0, 1, 2, or 3, or an external convert start signal. this flexibility allows the start of conver sion to be triggered by software events, a periodic signal (timer overflows), or extern al hw signals. conversion completions are indicated by a status bit and an interrupt (if enabled). the resu lting 10-bit data word is latched into the adc data sfrs upon completion of a conversion. window compare registers for the adc data can be conf igu red to interrupt the co ntroller when adc data is either within or outside of a specified range. the adc can monitor a key voltage continuously in back - ground mode, but not interrupt the controller unless the converted data is within/outside the specified range. capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 capture/compare module 4 / wdt cex1 eci crossbar cex2 cex3 cex4 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8
rev. 1.4 25 c8051f320/1 figure 1.10. 10-bit adc block diagram 1.10. comparators c8051f320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user software. port i/o pins may be configured as comparator inputs via a selection mux. two compar - ator outputs may be routed to a port pin if desired: a latch ed output and/or an unlatched (asynchronous) output. comparator response time is programmable, allowing the user to select between high-speed and low-power modes. positive and negative hysteresis are also configurable. comparator interrupts may be generated on rising, falling, or both edges. when in idle mode, these inter - rupts may be used as a ?wake-up? source. comparator0 may also be configured as a reset source. figure 1.11 shows the comparator0 block diagram. 10-bit sar adc timer 1 overflow cnvstr input timer 3 overflow (+) (-) configuration, control, and data registers 19-to-1 amux 19-to-1 amux p1.0 p1.7 p2.0 p2.7 p1.0 p1.7 p2.0 p2.7 p3.0 p3.0 p2.4-2.7 available on c8051f320 p2.4-2.7 available on c8051f320 analog multiplexer timer 0 overflow timer 2 overflow start conversion 000 ad0busy (w) 001 010 011 100 101 16 window compare logic window compare interrupt adc data registers end of conversion interrupt vdd temp sensor vref gnd
c8051f320/1 26 rev. 1.4 figure 1.11. comparator0 block diagram vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + p1.0 p1.4 p2.0 p2.4 cp0 - p1.1 p1.5 p2.1 p2.5 cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0mx cmx0n1 cmx0n0 cmx0p1 cmx0p0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 rising-edge cp0 falling-edge cp0 interrupt cp0rie cp0fie note: p2.4 and p2.5 available only on c8051f320
rev. 1.4 27 c8051f320/1 2. absolute maximum ratings table 2.1. absolute maximum ratings parameter conditions min typ max units ambient temperature under bias ?55 ? 125 c storage temperature ?65 ? 150 c voltage on any port i/o pin or /rst with res pect to gnd ?0.3 ? 5.8 v voltage on vdd with respect to gnd ?0.3 ? 4.2 v maximum total current through vdd and gnd ? ? 500 ma maximum output current sunk by /rst or any port pin ? ? 100 ma note: stresses above those listed under ?absolute maximum ra tings? may cause permanent damage to the device. this is a stress rating only and functional operation of th e devices at those or any other conditions above those indicated in the operation listings of th is specification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability.
c8051f320/1 28 rev. 1.4 3. global electrical characteristics table 3.1. global electrical characteristics ?40 to +85 c, 25 mhz system clock unless otherwise noted. parameter conditions min typ max units digital supply voltage v rst 1,2 3.0 3.6 v digital supply ram data retentio n voltage - 1.5 ? v sysclk (system clock) 3 0 ? 25 mhz t sysh (sysclk high time) 18 ? ? ns t sysl (sysclk low time) 18 ? ? ns specificed operating tem - perature range ?40 ? +85 c digital supply current - cpu active (normal mode, fetching instructions from flash) idd 4 v dd = 3.6 v; f = 25 mhz ? 12.3 13.6 ma v dd = 3.3 v, f = 24 mhz ? 10.6 11.5 ma v dd = 3.3 v, f = 6 mhz ? 3.2 ? ma v dd = 3.3 v, f = 32 khz ? 38 ? ua v dd = 3.0 v, f = 24 mhz ? 9.0 9.8 ma v dd = 3.0 v, f = 6 mhz ? 2.7 ? ma v dd = 3.0 v, f = 32 khz ? 32 ? ua idd supply sensitivity 4 f = 24 mhz ? 0.66 ? %/v f = 6 mhz ? 0.63 ? %/v idd frequency sensitivity 4 , 5 v dd = 3.0 v, f < 15 mhz, t = 25 c ? 0.45 ? ma/mhz v dd = 3.0 v, f > 15 mhz, t = 25 c ? 0.26 ? ma/mhz v dd = 3.3 v, f < 15 mhz, t = 25 c ? 0.53 ? ma/mhz v dd = 3.3 v, f > 15 mhz, t = 25 c ? 0.29 ? ma/mhz digital supply current - cpu and usb active (usb transceiver enabled and connected to pc) idd 4 v dd = 3.3 v, f = 24 mhz, full speed ? 16.8 ? ma v dd = 3.0 v, f = 24 mhz, full speed ? 14.4 ? ma v dd = 3.3 v, f = 6 mhz, low speed ? 7.2 ? ma v dd = 3.0 v, f = 6 mhz, low speed ? 6.0 ? ma digital supply current - cpu inactive (idle mode, not fetching instructions from flash) idle idd 4 v dd = 3.6 v; f = 25 mhz ? 5.8 6.5 ma v dd = 3.3 v, f = 24 mhz ? 5.2 5.9 ma v dd = 3.3 v, f = 6 mhz ? 1.7 ? ma v dd = 3.3 v, f = 32 khz ? 14 ? ua v dd = 3.0 v, f = 24 mhz ? 4.6 5.2 ma v dd = 3.0 v, f = 6 mhz ? 1.5 ? ma v dd = 3.0 v, f = 32 khz ? 11 ? ua
rev. 1.4 29 c8051f320/1 idle idd supply sensitivity 4 f = 24 mhz ? 0.47 ? %/v f = 6 mhz ? 0.50 ? %/v idle idd frequency ? sensitivity 4,6 v dd = 3.0 v, f < 1 mhz, t = 25 c ? 0.25 ? ma/mhz v dd = 3.0 v, f > 1 mhz, t = 25 c ? 0.17 ? ma/mhz v dd = 3.3 v, f < 1 mhz, t = 25 c ? 0.29 ? ma/mhz v dd = 3.3 v, f > 1 mhz, t = 25 c ? 0.20 ? ma/mhz digital supply current ? (stop mode) oscillator not running, v dd monitor disabled ? <0.1 ? a notes: 1. given in ta b l e 10.1, ?reset electrical chara cteristics,? on page 105 . 2. usb requ ires a minimum supply voltage of 3.0 v. 3. sysclk must be at least 32 khz to enable debugging. 4. base d on device characterization data; not production tested. 5. idd can be estimated for freq uencies < 15 mhz by simply multiplying the frequency of interest by the frequ ency sensitivity number for that range. w hen using these numbers to estimate idd for >15 mhz, the estimate should be the current at 24 mhz minus the difference in current i ndica ted by the frequency sensitivity number. for example: vdd = 3.0 v; f = 20 mhz, idd = 9.0 ma ? (24 mhz ? 20 mhz) x 0.26 ma/mhz = 7.96 ma. 6. idle idd can be estimated for frequencies < 1 mhz by simply multiplying the frequency of interest by the frequ ency sensitivity number for that range. when using these numbers to estimate idle idd for >1 mhz, the estimate should be the current at 24 mhz minus the difference in current i ndica ted by the frequency sensitivity number. for example: vdd = 3.0 v; f = 5 mhz, idle idd = 4.6 ma ? (24 mhz ? 5 mhz) x 0.17 ma/mhz = 1.37 ma. table 3.2. index to electrical characteristics tables peripheral electrical characteristics page # adc0 electrical characteristics 54 voltage reference electrical characteristics 56 comparator electrical characteristics 66 voltage regulator electrical characteristics 68 reset electrical characteristics 105 flash electrical characteristics 107 internal oscillator electrical characteristics 125 port i/o dc electrical characteristics 138 table 3.1. global electrical characteristics (continued) ?40 to +85 c, 25 mhz system clock unless otherwise noted. parameter conditions min typ max units
c8051f320/1 30 rev. 1.4 4. pinout and package definitions table 4.1. pin definitions for the c8051f320/1 name pin numbers type description ?f320 ?f321 vdd 6 6 power in power out 2.7-3.6 v power supply v oltage input. 3.3 v voltage regulator output. see section 8. gnd 3 3 ground. /rst/ c2ck 9 9 d i/o d i/o device reset. open-drain output of internal por or vdd mon itor. an external source can initiate a system reset by driving this pin low for at least 15 s. see section 10 . clock signal for the c2 debug interface. p3.0/ c2d 10 10 d i/o d i/o port 3.0. see section 14 for a complete description. bi-directional data signal for the c2 debug interface. regin 7 7 power in 5 v regulator input. this pin is the input to the on-chip volt - age regulator. vbus 8 8 d in vbus sense input. this pin should be connected to the vbus signal of a usb network. a 5 v signal on this pin indi - cates a usb network connection. d+ 4 4 d i/o usb d+. d- 5 5 d i/o usb d?. p0.0 2 2 d i/o port 0.0. see section 14 for a complete description of port 0. p0.1 1 1 d i/o port 0.1. p0.2/ xtal1 32 28 d i/o a in port 0.2. external clock input. this pin is the extern al oscillator return for a crystal or resonator. see section 13 . p0.3/ xtal2 31 27 d i/o a i/o or d in port 0.3. external clock output. this pin is the excitation driver for an external crystal or resonator, or an external clock input for cmos, capacitor, or rc os cillator configurations. see sec - tion 13 . p0.4 30 26 d i/o port 0.4. p0.5 29 25 d i/o port 0.5. p0.6/ cnvstr 28 24 port 0.6. adc0 external convert start input. see section 5 . p0.7/ vref 27 23 d i/o a i/o port 0.7. external vref inpu t or output. see section 6 . p1.0 26 22 d i/o or a in port 1.0. see section 14 for a complete description of port 1.
rev. 1.4 31 c8051f320/1 p1.1 25 21 d i/o or a in port 1.1. p1.2 24 20 d i/o or a in port 1.2. p1.3 23 19 d i/o or a in port 1.3. p1.4 22 18 d i/o or a in port 1.4. p1.5 21 17 d i/o or a in port 1.5. p1.6 20 16 d i/o or a in port 1.6. p1.7 19 15 d i/o or a in port 1.7. p2.0 18 14 d i/o or a in port 2.0. see section 14 for a complete description of port 2. p2.1 17 13 d i/o or a in port 2.1. p2.2 16 12 d i/o or a in port 2.2. p2.3 15 11 d i/o or a in port 2.3. p2.4 14 d i/o or a in port 2.4. p2.5 13 d i/o or a in port 2.5. p2.6 12 d i/o or a in port 2.6. p2.7 11 d i/o or a in port 2.7. table 4.1. pin definitions fo r the c8051f320/1 (continued) name pin numbers type description ?f320 ?f321
c8051f320/1 32 rev. 1.4 figure 4.1. lqfp-32 pi nout diagram (top view) 1 vbus p1.2 p1.7 p1.4 p1.3 p1.5 d+ d- gnd p0.1 p0.0 p2.0 p2.1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 p1.6 c8051f320 top view vdd regin /rst / c2ck p3.0 / c2d p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2
rev. 1.4 33 c8051f320/1 figure 4.2. lqfp- 32 package drawing table 4.2. lqfp-32 package dimensions dimension min nom max a ? ? 1.60 a1 0.05 ? 0.15 a2 1.35 1.40 1.45 b 0.30 0.37 0.45 c 0.09 ? 0.20 d 9.00 bsc. d1 7.00 bsc. e 0.80 bsc. e 9.00 bsc. e1 7.00 bsc. l 0.45 0.60 0.75
c8051f320/1 34 rev. 1.4 aaa 0.20 bbb 0.20 ccc 0.10 ddd 0.20 q 0 3.5 7 notes: 1. al l dimensions shown are in millimeters (mm) unless otherwise noted. 2. d imensioning and tolerancing per ansi y14.5m-1994. 3. thi s drawing conforms to jedec outline ms-026, variation bba. 4. r ecommended card reflow profile is per the jedec/ipc j-std- 020 specification for small body components. table 4.2. lqfp-32 packag e dimensions (continued) dimension min nom max
rev. 1.4 35 c8051f320/1 figure 4.3. lqfp-32 recommended pcb land pattern table 4.3. lqfp-32 pcb land pattern dimensions dimension min max dimension min max c1 8.40 8.50 x1 0.40 0.50 c2 8.40 8.50 y1 1.25 1.35 e 0.80 notes: general 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. t his land pattern design is based on the ipc-7351 guidelines. solder mask design 3. al l metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 4. a st ainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thic kness shoul d be 0.125mm (5 mils). 6. t he ratio of stencil aperture to land pad size should be 1:1 for all pads. card assembly 7. a no-cl ean, type-3 solder paste is recommended. 8. t he recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
c8051f320/1 36 rev. 1.4 figure 4.4. qfn-28 pino ut diagram (top view) 4 5 6 7 2 1 3 11 12 13 14 9 8 10 18 17 16 15 20 21 19 25 26 27 28 23 22 24 c8051f321 top view p0.1 p0.0 gnd d+ d- vdd regin vbus /rst / c2ck p3.0 / c2d p2.3 p2.2 p2.1 p2.0 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 gnd
rev. 1.4 37 c8051f320/1 figure 4.5. qfn-28 package drawing table 4.4. qfn-28 package dimensions dimension min typ max dimension min typ max a 0.80 0.90 1.00 l 0.35 0.55 0.65 a1 0.00 0.02 0.05 l1 0.00 ? 0.15 a3 0.25 ref aaa 0.15 b 0.18 0.23 0.30 bbb 0.10 d 5.00 bsc. ddd 0.05 d2 2.90 3.15 3.35 eee 0.08 e 0.50 bsc. z 0.44 e 5.00 bsc. y 0.18 e2 2.90 3.15 3.35 notes: 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. d imensioning and tolerancing per ansi y14.5m-1994. 3. this draw ing conforms to the jedec solid state outline mo-220, variation vhhd except for custom features d2, e2, z, y, and l wh ich are toleranced per supplier designation. 4. r ecommended card reflow profile is per the jede c/ipc j-std-020 specific ation for small body components.
c8051f320/1 38 rev. 1.4 figure 4.6. qfn-28 recomm ended pcb land pattern table 4.5. qfn-28 p cb land pattern dimesions dimension min max dimension min max c1 4.80 x2 3.20 3.30 c2 4.80 y1 0.85 0.95 e 0.50 y2 3.20 3.30 x1 0.20 0.30 notes: general 1. al l dimensions shown are in millim eters (mm) unless otherwise noted. 2. d imensioning and tolerancing is per the ansi y14.5m-1994 specification. 3. t his land pattern design is based on the ipc-7351 guidelines. solder mask design 4. al l metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 ? m minimum, all the way around the pad. stencil design 5. a st ainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 6. the stencil thic kness shoul d be 0.125mm (5 mils). 7. t he ratio of stencil aperture to land pad size should be 1:1 for all perimeter pins. 8. a 3x3 array of 0.9 0mm openings on a 1.1mm pitch should be used for the center pad to assure the proper paste volume (67% paste coverage). card assembly 9. a no-cl ean, type-3 solder paste is recommended. 10. t he recommended card reflow profile is per th e jedec/ipc j-std-020 specification for small body components.
rev. 1.4 39 c8051f320/1 5. 10-bit adc (adc0) the adc0 subsystem for the c8051f320 /1 consists of two analog multiple xers (referred to collectively as amux0) with 17 total inpu t selections, and a 200 ksps, 10-bit successive-app roxima tion- register adc with integrated track-and-hold and programmable window detector. the amux0, data conversion modes, and window detector are all configurable under software control via the special function registers shown in figure 5.1 . adc0 operates in both single-ended and differential modes, and may be configured to mea - sure p1.0-p3.0, the temperature sensor output, or vdd with respec t to p1.0- p3.0, vref, or gnd. the adc0 subsystem is enabled only when the ad0en bit in the adc0 control regist er (adc0cn) is set to logic 1. the adc0 subsystem is in low powe r shut dow n when this bit is logic 0. adc0cf ad0ljst ad0sc0 ad0sc1 ad0sc2 ad0sc3 ad0sc4 10-bit sar adc ref sysclk adc0h 32 adc0cn ad0cm0 ad0cm1 ad0cm2 ad0wint ad0busy ad0int ad0tm ad0en timer 0 overflow timer 2 overflow timer 1 overflow start conversion 000 ad0busy (w) vdd adc0lth 19-to-1 amux ad0wint 001 010 011 100 cnvstr input window compare logic gnd p1.0 p1.7 p2.0 p2.7 p3.0 101 timer 3 overflow adc0ltl adc0gth adc0gtl adc0l amx0p amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 amx0n amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 (+) (-) vref p2.4-2.7 available on c8051f320 temp sensor 19-to-1 amux p1.0 p1.7 p2.0 p2.7 p3.0 p2.4-2.7 available on c8051f320 vdd figure 5.1. adc0 functional block diagram
c8051f320/1 40 rev. 1.4 5.1. analog multiplexer amux0 selects the positive and negative inputs to th e adc. any of the following may be selected as the positive input: p1.0-p3.0, the on-chip temperature sensor, or the positive power supply (v dd ). any of the following may be selected as the negative input: p1.0-p3.0, vref, or gnd. when gnd is selected as the negative input, adc0 operate s in single-ended mode ; all other times, adc0 operates in differ - ential mode. the adc0 input channels are selected in t he amx0p and amx0n registers as described in figure 5.2 and figure 5.2 . the conversion code format differs between single -en ded and differential modes. the registers adc0h and adc0l contain the high and low bytes of the output conversion code from the adc at the completion of each conversion. data can be right-justified or left -justified, depending on the setting of the ad0ljst bit (adc0cn.0). when in single-ended mode, conversion codes are represented as 10-bit unsigned integers. inputs are measured from ?0? to vref x 1023/1024. example codes are shown below for both right-justi - fied and left-justified data. unused bits in the adc0h and adc0l registers are set to ?0?. when in differential mode, conversion codes are represented as 10-bit signed 2?s complement numbers. inp uts are measured from ?vref to vref x 511/512. example codes are shown below for both right-jus - tified and left-justified data. for right-justified data, the unused msbs of adc0h are a sign-extension of the data word. for left-justified data, the unused lsbs in the adc0l register are set to ?0?. important note about adc0 input configuration: por t pins selected as adc0 inputs should be config - ured as analog inputs, and should be skipped by the dig ital crossbar. to configure a port pin for analog input, set to ?0? the corresponding bit in register pnmd in (for n = 0,1,2,3). to fo rce the crossbar to skip a port pin, set to ?1? the corresponding bi t in register pnskip (for n = 0,1,2). see section ?14. port input/out - put? on page 126 for more port i/o configuration details. input voltage ( single-ended) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 1023/1024 0x03ff 0xffc0 vref x 512/1024 0x0200 0x8000 vref x 256/1024 0x0100 0x4000 0 0x0000 0x0000 input voltage (differential) right-justified adc0h:adc0l (ad0ljst = 0) left-justified adc0h:adc0l (ad0ljst = 1) vref x 511/512 0x01ff 0x7fc0 vref x 256/512 0x0100 0x4000 0 0x0000 0x0000 ?vref x 256/512 0xff00 0xc000 ?vref 0xfe00 0x8000
rev. 1.4 41 c8051f320/1 5.2. temperature sensor the temperature sensor transfer function is shown in figure 5.2 . the output voltage (v temp ) is the positive adc input when the temperature sensor is selected by bits amx0p4-0 in register amx0p. values for the of fset and slope parameters can be found in ta b l e 5.1 . temperature voltage v temp = ( gain x temp c ) + offset offset (v at 0 celsius) gain (v / deg c) temp c = (v temp - offset ) / gain figure 5.2. temperature sensor transfer function the uncalibrated temperature sensor output is extrem ely linear and suitable for relative temperature mea - surements (see ta b l e 5.1 for linearity specifications). for absolu te tem per ature measurements, offset and/ or gain calibration is recommended. typically a 1-po int (of f set) calibration in cludes the following steps: step 1. control/measure the ambient temper atur e ( this temperature must be known). step 2. power the device, and delay for a few seconds to allow for self-heating. step 3. perform an adc conversion with the te mperature sensor selected as the positive input and gnd selected as the negative input. step 4. calculate the offset characteristics, a nd store this value in non-volatile memory for use with subsequent temperatur e sensor measurements. figure 5.3 shows the typical temperature sensor er ror assumin g a 1-point calibration at 25 c. note that p arameters which affect adc measurement, in particular the voltage reference value, will also a ff ect temperature measurement.
-40.00 -20.00 0.0 0 20.0 0 40.0 0 60.0 0 80.0 0 temperature (degrees c) error (degrees c) -5.00 -4.00 -3.00 -2.00 -1.00 0.0 0 1.0 0 2.0 0 3.0 0 4.0 0 5.0 0 -5.00 -4.00 -3.00 -2.00 -1.00 0.0 0 1.0 0 2.0 0 3.0 0 4.0 0 5.0 0 c8051f320/1 42 rev. 1.4 figure 5.3. temperature sensor error with 1-point calibration (vref = 2.40 v)
rev. 1.4 43 c8051f320/1 5.3. modes of operation adc0 has a maximum conversion speed of 200 ksps. the adc0 conversion clock is a divided version of the system clock, determined by the ad0sc bits in the adc0cf register (system clock divided by (ad0sc + 1) for 0 ? ad0sc ? ? 31). 5.3.1. starting a conversion a conversion can be initiated in one of five ways, dep ending on the programmed states of the adc0 start of conversion mode bits (ad0cm2?0) in register adc0 cn. conversions may be initiated by one of the fol - lowing: 1. writing a ?1? to the ad0busy bit of register adc0cn 2. a timer 0 overflow (i.e., timed co ntinuous conversions) 3. a timer 2 overflow 4. a timer 1 overflow 5. a rising edge on the cnvstr input signal (pin p0.6) 6. a timer 3 overflow writing a ?1? to ad0busy provides software contro l of adc0 whereby conversions are performed "on- demand". during conversion, the ad0busy bit is set to lo gic 1 and reset to logic 0 when the conversion is complete. the falling edge of ad0bu sy triggers an interrupt (when enabl ed) and sets the adc0 interrupt flag (ad0int). note: when polling for adc conversion completions, the adc0 in terrupt flag (ad0int) should be used. converted data is available in th e adc0 data registers, adc0h:adc0l, when bit ad0int is logic 1. note that when timer 2 or timer 3 overfl ows are used as the conversion source, low byte over - flows are used if timer 2/3 is in 8-bit mode; high byte over flows are used if timer 2/3 is in 16-bit mode. see section ?19. timers? on page 209 for timer configuration. important note about using cnvstr: th e cnvstr input pin also functions as port pin p0.6. when the cnvstr input is used as the adc0 conversion source, port pin p0.6 should be skipped by the digital crossbar. to configure the crossbar to skip p0 .6, set to ?1? bit6 in register p0skip. see section ?14. port input/output? on page 126 for details on port i/o configuration.
c8051f320/1 44 rev. 1.4 5.3.2. tracking modes the ad0tm bit in register adc0cn controls the adc0 track-and-hold mode. in its default state, the adc0 input is continuously tracked, except when a conversi on is in progress. when the ad0tm bit is logic 1, adc0 operates in low-power track-and-hold mode. in this mode, each conversion is preceded by a track - ing period of 3 sar clocks (after the start-of-convers ion s i gnal). when the cnvstr signal is used to initi - ate conversions in low-power tracking mode, adc0 tr ac ks only when cnvstr is low; conversion begins on the rising edge of cnvstr (see figure 5.4 ). tracking can also be disabled (shutdown) when the device is in low power standby or sleep mod e s. low-power track-and-hold mode is also useful when amux set - tings are frequently changed, due to the settling time requirements described in section ?5.3.3. settling time requirements? on page 45. write '1' to ad0busy, timer 0, timer 2, timer 1, timer 3 overflow (ad0cm[2:0] = 000, 001,010 011, 101) ad0tm = 1 track convert low power mode ad0tm = 0 track or convert convert track low power or convert sar clocks 123456789101112 123456789 sar clocks b. adc0 timing for internal trigger source 123456789 cnvstr (ad0cm[2:0] = 100) ad0tm = 1 a. adc0 timing for external trigger source sar clocks track or convert convert track ad0tm = 0 track convert low power mode low power or convert 10 11 13 14 10 11 12 13 14 15 16 17 12 13 14 figure 5.4. 10-bit adc track and conversion example timing
rev. 1.4 45 c8051f320/1 5.3.3. settling time requirements when the adc0 input configuration is changed (i.e., a different amux0 selection is made), a minimum tracking time is required before an accurate conversion can be performed. this tracking time is determined by the amux0 resistance, the adc0 sampling capacita nce, any external source resistance, and the accu - racy required for the conversion. note that in low-po we r tr acking mode, three sar clocks are used for tracking at the start of every conv ersion. for most applications, these three sar clocks will meet the mini - mum tracking time requirements. figure 5.5 shows the equivalent adc0 input circuits for b o th differential and single-ended modes. notice that the equivalent time constant for both input circ uit s is the same. the required adc0 settling time for a given settling accuracy (sa) may be approximated by equation 5.1 . when measuring the temperature sensor output or vdd with respect to gnd, r total reduces to r mux . see ta b l e 5.1 for adc0 minimum settling time requirements. equation 5.1. adc0 settling time requirements t 2 n sa ------ - ?? ?? r total c sample ? where: sa is the settling accuracy, given as a fraction of an lsb (for example, 0.25 to settle within 1/4 lsb) t is the r equired settling time in seconds r total is the sum of the amux0 resistance and any external source resistance. n is the ad c resolution in bits (10). r mux = 5k rc input = r mux * c sample r mux = 5k c sample = 5pf c sample = 5pf mux select mux select differential mode px.x px.x r mux = 5k c sample = 5pf rc input = r mux * c sample mux select single-ended mode px.x figure 5.5. adc0 eq uivalent input circuits
c8051f320/1 46 rev. 1.4 sfr definition 5.1. bits7?5: unused. read = 000b; write = don?t care. bits4?0: amx0p4?0: amux0 positive input selection r r r r/w r/w r/w r/w r/w reset value - - - amx0p4 amx0p3 amx0p2 amx0p1 amx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbb amx0p4?0 adc0 positive input 00000 p1.0 00001 p1.1 00010 p1.2 00011 p1.3 00100 p1.4 00101 p1.5 00110 p1.6 00111 p1.7 01000 p2.0 01001 p2.1 01010 p2.2 01011 p2.3 01100* p2.4* 01101* p2.5* 01110* p2.6* 01111* p2.7* 10000 p3.0 10001?11101 reserved 11110 temp sensor 11111 vdd *note: only applies to c8051f320; selection reserved on c8051f321 devices. amx0p: amux0 positive channel select
rev. 1.4 47 c8051f320/1 sfr definition 5.2. bits7?5: unused. read = 000b; write = don?t care. bits4?0: amx0n4?0: amux0 negative input selection. note that when gnd is selected as the ne gative input, adc0 operates in single-ended mode. for all other negative input selectio ns, adc0 operates in differential mode. r r r r/w r/w r/w r/w r/w reset value - - - amx0n4 amx0n3 amx0n2 amx0n1 amx0n0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xba amx0n4?0 adc0 negative input 00000 p1.0 00001 p1.1 00010 p1.2 00011 p1.3 00100 p1.4 00101 p1.5 00110 p1.6 00111 p1.7 01000 p2.0 01001 p2.1 01010 p2.2 01011 p2.3 01100* p2.4* 01101* p2.5* 01110* p2.6* 01111* p2.7* 10000 p3.0 10001?11101 reserved 11110 vref 11111 gnd (adc in single-ended mode) *note: only applies to c8051f 320; selection reserved on c8051f321 devices. amx0n: amux0 negative channel select
c8051f320/1 48 rev. 1.4 sfr definition 5.3. bits7?3: ad0sc4?0: adc0 sar conversion clock period bits. sar conversion clock is derived from system clock by the following equation, where ad0sc refers to the 5-bit value held in bits ad0sc4-0. sar conversion clock requirements are given in table 5.1. bit2: ad0ljst: adc0 left justify select. 0: data in adc0h:adc0l registers are right-justified. 1: data in adc0h:adc0l r egisters are left-justified. bits1?0: unused. read = 00b; write = don?t care. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0sc4 ad0sc3 ad0sc2 ad0sc1 ad0sc0 ad0ljst - - 11111000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbc ad0sc sysclk clk sar --------------------- - 1? = adc0cf: adc0 configuration sfr definition 5.4. bits7?0: adc0 data word high-order bits. for ad0ljst = 0: bits 7-2 are the sign extension of bit1. bits 1?0 are the upper 2 bits of the 10-bit adc0 data word. for ad0ljst = 1: bits 7?0 are the most-signifi cant bits of the 10-bit adc0 data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbe adc0h: adc0 data word msb sfr definition 5.5. bits7?0: adc0 data word low-order bits. for ad0ljst = 0: bits 7?0 are the lower 8 bits of the 10-bit data word. for ad0ljst = 1: bits 7?6 are the lower 2 bits of the 10-bit data word. bits 5?0 will always read ?0?. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xbd adc0l: adc0 data word lsb
rev. 1.4 49 c8051f320/1 sfr definition 5.6. bit7: ad0en: adc0 enable bit. 0: adc0 disabled. adc0 is in low-power shutdown. 1: adc0 enabled. adc0 is active and ready for data conversions. bit6: ad0tm: adc0 track mode bit. 0: normal track mode: when adc0 is enabled, tracking is continuous unless a conversion is in progress. 1: low-power track mode: tracking defined by ad0cm2-0 bits (see below). bit5: ad0int: adc0 conversi on complete interrupt flag. 0: adc0 has not completed a data conversion since the last time ad0int was cleared. 1: adc0 has completed a data conversion. bit4: ad0busy: adc0 busy bit. read: 0: adc0 conversion is complete or a conversion is not currently in progress. ad0int is set to logic 1 on the falling edge of ad0busy. 1: adc0 conversion is in progress. write: 0: no effect. 1: initiates adc0 conversion if ad0cm2?0 = 000b bit3: ad0wint: adc0 window compare interrupt flag. 0: adc0 window comparison data match has no t occurred since this flag was last cleared. 1: adc0 window comparison data match has occurred. bits2?0: ad0cm2?0: adc0 start of conversion mode select. when ad0tm = 0: 000: adc0 conversion initiated on every write of ?1? to ad0busy. 001: adc0 conversion initiated on overflow of timer 0. 010: adc0 conversion initiated on overflow of timer 2. 011: adc0 conversion initiated on overflow of timer 1. 100: adc0 conversion initiated on rising edge of external cnvstr. 101: adc0 conversion initiated on overflow of timer 3. 11x: reserved. when ad0tm = 1: 000: tracking initiated on write of ?1? to ad0busy and lasts 3 sar clocks, followed by conver- sion. 001: tracking initiated on overflow of timer 0 and lasts 3 sar clocks, followed by conversion. 010: tracking initiated on overflow of timer 2 and lasts 3 sar clocks, followed by conversion. 011: tracking initiated on overflow of timer 1 and lasts 3 sar clocks, followed by conversion. 100: adc0 tracks only when cnvstr input is logic low; conversion starts on rising cnvstr edge. 101: tracking initiated on overflow of timer 3 and lasts 3 sar clocks, followed by conversion. 11x: reserved. r/w r/w r/w r/w r/w r/w r/w r/w reset value ad0en ad0tm ad0int ad0busy ad0wi nt ad0cm2 ad0cm1 ad0cm0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe8 adc0cn: adc0 control
c8051f320/1 50 rev. 1.4 5.4. programmable window detector the adc programmable window detector continuously compares the adc0 conver sion results to user- programmed limits, and notifies the system when a desired condition is detected. th is is especially effec - tive in an interrupt-driven system, saving code spac e and cpu bandwid th while delivering fast er system response times. the window detector interrupt flag (ad0wint in register adc0cn) can also be used in polled mode. the adc0 greater-than (adc0gth, adc0gtl) and less-than (adc0lth, adc0ltl) registers hold the comparison valu es. the window detector flag can be programmed to indicate when mea - sured data is inside or outside of the user-progr am med limits, depending on the contents of the adc0 less-than and adc0 greater-than registers. the window detector registers must be written with the same for mat (left/right ju stified, signed/unsigned) as that of the current adc configuration (lef t/right justified, sing le-ended/differential). sfr definition 5.7. bits7?0: high byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc4 adc0gth: adc0 greater-than data high byte sfr definition 5.8. bits7?0: low byte of adc0 greater-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc3 adc0gtl: adc0 grea ter-than data low byte
rev. 1.4 51 c8051f320/1 sfr definition 5.9. bits7?0: high byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc6 adc0lth: adc0 less-than data high byte sfr definition 5.10. bits7?0: low byte of adc0 less-than data word. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc5 adc0ltl: adc0 less-than data low byte
c8051f320/1 52 rev. 1.4 5.4.1. window detector in single-ended mode figure 5.6 shows two example window comparisons fo r ri ght-justified, single-ended data, with adc0lth:adc0ltl = 0x0080 (128d) and adc0gth:adc0gtl = 0x0040 (64d). in single-ended mode, the in put voltage can range from ?0? to vref * (1023/ 1024) with respect to gnd, and is represented by a 10-bit unsigned integer va lue. in the left example, an ad0wint interrupt will be generated if the adc0 conversion word (adc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0x0040 < adc0h:adc0l < 0x0080). in the right example, and ad0wint interrupt will be generated i f the adc0 conversion word is outside of the range defi ned by the adc0gt and adc0lt registers (if adc0h:adc0l < 0x0040 or adc0h:adc0l > 0x0080). figure 5.7 shows an exam - ple using left-justified data with equivale nt adc0gt and adc0lt register settings. 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0x03ff 0x0081 0x0080 0x007f 0x0041 0x0040 0x003f 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl 0xffc0 0x2040 0x2000 0x1fc0 0x1040 0x1000 0x0fc0 0x0000 0 input voltage (px.x - gnd) vref x (1023/1024) vref x (128/1024) vref x (64/1024) ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl adc0gth:adc0gtl figure 5.6. adc window co mpare example: right-justified single-ended data figure 5.7. adc window co mpare example: lef t-justified single-ended data
rev. 1.4 53 c8051f320/1 5.4.2. window detector in differential mode figure 5.8 shows two example window comparisons for ri ght-justified, differential data, with adc0lth:adc0ltl = 0x0040 (+64d) and adc0gth:adc0gth = 0xffff (-1d). in differential mode, the me asur able voltage between the input pins is between -vref and vref*(511/512). output codes are rep - resented as 10-bit 2?s complement s igned integers . in the left example, an ad 0wint interrupt will be gen - erated if the adc0 conversion wo rd (a dc0h:adc0l) is within the range defined by adc0gth:adc0gtl and adc0lth:adc0ltl (if 0xffff (-1d) < adc0h:adc0l < 0x0040 (64d)). in the ri g h t example, an ad0wint interrupt will be generated if the adc0 conversion word is ou tside of the range defined by the adc0gt and adc0lt registers (if adc0h:adc0l < 0xffff (-1d) or adc0h:adc0l > 0x0040 (+64d)). figure 5.9 shows an example using left-justified data with equivalent adc0gt and adc0lt register set - tings. 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) 0x01ff 0x0041 0x0040 0x003f 0x0000 0xffff 0xfffe 0x0200 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0gth:adc0gtl adc0lth:adc0ltl 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.y) vref x (511/512) vref x (64/512) vref x (-1/512) 0x7fc0 0x1040 0x1000 0x0fc0 0x0000 0xffc0 0xff80 0x8000 -vref input voltage (px.x - px.x) vref x (511/512) vref x (64/512) vref x (-1/512) ad0wint=1 ad0wint not affected ad0wint not affected adc0lth:adc0ltl adc0gth:adc0gtl ad0wint not affected adc0gth:adc0gtl ad0wint=1 ad0wint=1 adc0h:adc0l adc0h:adc0l adc0lth:adc0ltl figure 5.8. ad c window compare example: righ t-justified differential data figure 5.9. adc window compare exampl e: left-justified differential dat a
table 5.1. adc0 electrical characteristics v dd = 3.0 v, vref = 2.40 v, ?40 to +85 c unless otherwise specified. parameter conditions min typ max units dc accuracy resolution 10 bits integral nonlinearity ? 0.5 1 lsb differential nonlinearity guaranteed monotonic ? 0.5 1 lsb offset error ?15 0 15 lsb full scale error ?15 ?1 15 lsb offset temperature coefficient ? 10 ? ppm/c dynamic performance (10 khz sine-wave sing le -e nded input, 1 db below full scale, 200 ksps) signal-to-noise plus distortion 53 55.5 ? db total harmonic distortion up to the 5 th harmonic ? ?67 ? db spurious-free dynamic range ? 78 ? db conversion rate sar conversion clock ? ? 3 mhz conversion time in sar clocks 10 ? ? clocks track/hold acquisition time 300 ? ? ns throughput rate ? ? 200 ksps analog inputs adc input voltage range single ended (ain+ ? gnd) differential (ain+ ? ain?) 0 ?vref ? vref vref v v absolute pin voltage with respect to gnd sin gle ended or differential 0 ? vdd v input capacitance ? 5 ? pf temperature sensor ? ? ? linearity 1 ? 0.1 ? c gain 2 ? 2.86 ? mv/c offset 1,2 (temp = 0 c) ? 0.776 8.5 ? mv power specifications power supply current ? (v dd supplied to adc0) operating mode, 200 ksps ? 400 900 a power supply rejection ? 0.3 mv/v notes: 1. includes adc offset, gain, and linearity variations. 2. represents one standard deviation from the mean. c8051f320/1 54 rev. 1.4
rev. 1.4 55 c8051f320/1 6. voltage reference the voltage reference mux on c8051f320/1 devices is configurable to use an externally connected volt - age reference, the internal reference voltage generator, or the power supply voltage vdd (see figure 6.1 ). the refsl bit in the reference control register (ref0cn) selects the reference source. for the internal r e ference or an external source, refsl should be set to ?0?; for vdd as the reference source, refsl should be set to ?1?. the biase bit enables the inte rnal adc bias generator , wh ich is used by the adc and internal oscillator. this enable is forced to logic 1 when either of t he aforementioned peripherals is enabled. the adc bias generator may be enabled manually by writ ing a ?1? to the biase bit in register ref0cn; see figure 6.1 for ref0cn register details. the re fe re nce bias generator (see figure 6.1 ) is used by the internal voltage reference, temperature sensor, and clock multiplier. the reference bias is automatically enabled when a n y of the aforementioned peripherals are enabled. the electrical specifications for the voltage reference and bias circuits are given in ta b l e 6.1 . important note about the vref input: por t pin p0.7 is used as the external vref input. when using an external voltage reference, p0.7 should be configured as analog input and skipped by the digital crossbar. to configure p0.7 as analog input, se t to ?0? bit7 in register p0mdin. to configure the crossbar to skip p0.7, set to ?1? bit7 in register p0skip. refer to section ?14. port input/output? on page 126 for complete port i/o configuration details. the temperature sensor connects to the adc 0 positive input multiplexer (see section ?5.1. analog multi - plexer? on page 40 for details). the tempe bit in register ref 0 cn enables/disables the temperature sen - sor. while disabled, the temperature sensor defaults to a high impedance state and any adc0 me asur ements performed on the sensor result in meaningless data. vref (to adc) to analog mux vdd vref r1 vdd external voltage reference circuit gnd temp sensor en 0 1 ref0cn refsl tempe biase refbe refbe internal reference en reference bias en clkmul enable tempe to clock multiplier, temp sensor adc bias to adc, internal oscillator en ioscen ad0en figure 6.1. voltage refere nce functional block diagram
c8051f320/1 56 rev. 1.4 sfr definition 6.1. bits7?3: unused. read = 00000b; write = don?t care. bit3: refsl: voltage reference select. this bit selects the source for the internal voltage reference. 0: vref pin used as voltage reference. 1: vdd used as voltage reference. bit2: tempe: temperature sensor enable bit. 0: internal temperature sensor off. 1: internal temperature sensor on. bit1: biase: internal analog bias generator enable bit. 0: internal bias generator off. 1: internal bias generator on. bit0: refbe: internal refe rence buffer enable bit. 0: internal reference buffer disabled. 1: internal reference buffer enabled. internal voltage reference driven on the vref pin. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - refsl tempe biase refbe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd1 ref0cn: reference control table 6.1. voltage reference electrical characteristics v dd = 3.0 v; ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal reference (refbe = 1) output voltage 25 c ambient 2.38 2.44 2.50 v vref short-circuit current 10 ma vref temperature coeffi - cient 15 ppm/c load regulation load = 0 to 200 a to gnd 1.5 ppm/a vref turn-on time 1 4.7 f tantalum, 0.1 f ceramic bypass 2 ms vref turn-on time 2 0.1 f ceramic bypass 20 s vref turn-on time 3 no bypass cap 10 s power supply rejection 140 ppm/v external reference (refbe = 0) input voltage range 0 vdd v input current sample rate = 200 ksps; vref = 3.0 v 12 a bias generators adc bias generator biase = ?1? 106 148 a reference bias generator 42 60 a
rev. 1.4 57 c8051f320/1 7. comparators c8051f320/1 devices include two on-chip programmable voltage comparators: comparator0 is shown in figure 7.1 ; comparator1 is shown in figure 7.2 . the two comparators operate identically with the follow - ing exceptions: (1) their input selections differ as shown in figure 7.1 and figure 7.2 ; (2) comparator0 can be used as a reset source. each comparator offers programmable response time and hysteresis, an analog input multiplexer, and two o u tputs that are optionally available at the port pins : a synchronous ?latched? output (cp0, cp1), or an asynchronous ?raw? output (cp0a, cp1a). the asynchronous signal is available even when the system clock is not active. this allows the comparators to operate and generate an output with the device in stop mode. when assigned to a port pin, the comparator outputs may be configured as open drain or push-pull (see section ?14.2. port i/o initializa t ion? on page 130 ). comparator0 may also be used as a reset source (see section ?10.5. comparator0 reset? on page 102 ). the comparator0 inputs are selected in the cpt0mx register ( figure 7.2 ). the cmx0p1?cmx0p0 bits select the comparator0 positive input; the cmx0n1?c mx0n0 b i ts select the comparator0 negative input. the comparator1 inputs are selected in the cpt1mx register ( figure 7.5 ). the cmx1p1?cmx1p0 bits select the comparator1 positive input; the cmx1n1?cmx 1 n 0 bits select the comparator1 negative input. important note about comparator inputs: th e por t pins selected as comparator inputs should be con - figured as analog inputs in their associated port co nfigur ation register, and configured to be skipped by the crossbar (for details on port configuration, see section ?14.3. general purpose port i/o? on page 132 ). vdd cpt0cn reset decision tree + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp0 + p1.0 p1.4 p2.0 p2.4 cp0 - p1.1 p1.5 p2.1 p2.5 cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 cpt0mx cmx0n1 cmx0n0 cmx0p1 cmx0p0 cpt0md cp0rie cp0fie cp0md1 cp0md0 cp0 cp0a cp0 rising-edge cp0 falling-edge cp0 interrupt cp0rie cp0fie note: p2.4 and p2.5 available only on c8051f320 figure 7.1. comparator0 functional block diagram
c8051f320/1 58 rev. 1.4 comparator outputs can be polled in software, used as an interrupt source, and/or routed to a port pin. when routed to a port pin, compar ator outputs are availa ble asynchronous or syn chronous to the system clock; the asynchronous output is available even in stop mode (with no system clock active). when dis - abled, the comparator output (if assigned to a port i/o pin via th e cr ossbar) defaults to the logic low state, and supply current falls to less than 100 na. see section ?14.1. priority crossbar decoder? on page 128 for details on configuring comparator outputs via the di git a l crossbar. comparator inputs can be externally driven from ?0.25 v to (v dd ) + 0.25 v without damage or upset. the complete comparator electrical spec - ifications are given in ta b l e 7.1 . comparator response time may be configured in software via the cptnmd registers (see figure 7.3 and figure 7.6 ). selecting a longer response time reduces the comparator supply current. see ta b l e 7.1 for complete timing and supply current specifications. vdd cpt1cn + - crossbar interrupt logic q q set clr d q q set clr d (synchronizer) gnd cp1 + p1.2 p1.6 p2.2 p2.6 cp1 - p1.3 p1.7 p2.3 p2.7 cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 cpt1mx cmx1n1 cmx1n0 cmx1p1 cmx1p0 cpt1md cp1rie cp1fie cp1md1 cp1md0 cp1 cp1a cp1 rising-edge cp1 falling-edge cp1 interrupt cp1rie cp1fie note: p2.6 and p2.7 available only on c8051f320 figure 7.2. comparator1 functional block diagram
positive hysteresis voltage (programmed with cp0hyp bits) negative hysteresis voltage (programmed by cp0hyn bits) vin- vin+ inputs circuit configuration + _ cp0+ cp0- cp0 vin+ vin- out v oh positive hysteresis disabled maximum positive hysteresis negative hysteresis disabled maximum negative hysteresis output v ol comparator hysteresis is programmed using bits3?0 in the comparator control register cptncn (shown in figure 7.1 and figure 7.4 ). the amount of negative hysteresis vo lt a ge is determined by the settings of the cpnhyn bits. as shown in figure 7.3 , settings of 20, 10 or 5 mv of negative hysteresis can be programmed, or negative hysteresis can be disabled. in a sim ilar way, the amount of positive hysteresis is determined by the setting the cpnhyp bits. comparator interrupts can be genera ted on both rising-e dge and falling-edge output transitions. (for inter - rupt enable and priority control, see section ?9.3. interrupt handler? on page 87 .) the cpnfif flag is set to ?1? upon a comparator falling- edge, and the cpnrif flag is set to ?1 ? upon the comparat or rising-edge. once set, these bits remain set until cleared by so ftware. the output state of the comparator can be obtained at any time by reading the cpnout bit. th e comparator is enabled by setting the cpnen bit to ?1?, and is disabled by clearing this bit to ?0?. rev. 1.4 59 c8051f320/1 figure 7.3. compar ator hysteresis plot
c8051f320/1 60 rev. 1.4 sfr definition 7.1. cpt0cn: comparator0 control bit7: cp0en: comparator0 enable bit. 0: comparator0 disabled. 1: comparator0 enabled. bit6: cp0out: comparator0 output state flag. 0: voltage on cp0+ < cp0?. 1: voltage on cp0+ > cp0?. bit5: cp0rif: comparator0 rising-edge flag. 0: no comparator0 rising edge has occu rred since this flag was last cleared. 1: comparator0 rising edge has occurred. bit4: cp0fif: comparator0 falling-edge flag. 0: no comparator0 falling-edge has occu rred since this flag was last cleared. 1: comparator0 fa lling-edge interrupt has occurred. bits3?2: cp0hyp1?0: comparator0 posi tive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp0hyn1?0: comparator0 nega tive hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp0en cp0out cp0rif cp0fif cp0hyp1 cp0hyp0 cp0hyn1 cp0hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9b
rev. 1.4 61 c8051f320/1 sfr definition 7.2. cpt0mx: comparator0 mux selection bits7?6: unused. read = 00b, write = don?t care. bits5?4: cmx0n1?cmx0n0: comparat or0 negative input mux select. these bits select which port pin is used as the comparator0 negative input. bits3?2: unused. read = 00b, write = don?t care. bits1?0: cmx0p1?cmx0p0: comparator0 positive input mux select. these bits select which port pin is used as the comparator0 positive input. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - cmx0n1 cmx0n0 - - cm x0p1 cmx0p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9f cmx0n1 cmx0n0 negative input 00 p1.1 01 p1.5 10 p2.1 11 p2.5* cmx0p1 cmx0p0 positive input 00 p1.0 01 p1.4 10 p2.0 11 p2.4* *note: p2.4 and p2.5 available only on c8051f320 devices; selection reserved on c8051f321 devices.
c8051f320/1 62 rev. 1.4 sfr definition 7.3. cpt0md: comparator 0 mode selection bits7?6: unused. read = 00b. write = don?t care. bit5: cp0rie: comparator0 rising-edge interrupt enable. 0: comparator0 rising-edge interrupt disabled. 1: comparator0 rising-edge interrupt enabled. bit4: cp0fie: comparator0 falling-edge interrupt enable. 0: comparator0 falling-e dge interrupt disabled. 1: comparator0 falling-e dge interrupt enabled. bits3?2: unused. read = 00b. write = don?t care. bits1?0: cp0md1?cp0md0: comparator0 mode select these bits select the response time for comparator0. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - cp0rie cp0fie - - cp0md1 cp0md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9d mode cp0md1 cp0md0 cp0 response time (typ) 000 100 ns 101 175 ns 210 320 ns 3 1 1 1050 ns
rev. 1.4 63 c8051f320/1 sfr definition 7.4. cpt1cn: comparator1 control bit7: cp1en: comparator1 enable bit. 0: comparator1 disabled. 1: comparator1 enabled. bit6: cp1out: comparator1 output state flag. 0: voltage on cp1+ < cp1?. 1: voltage on cp1+ > cp1?. bit5: cp1rif: comparator1 rising-edge flag. 0: no comparator1 rising edge has occu rred since this flag was last cleared. 1: comparator1 rising edge has occurred. bit4: cp1fif: comparator1 falling-edge flag. 0: no comparator1 falling-edge has occu rred since this flag was last cleared. 1: comparator1 falling- edge has occurred. bits3?2: cp1hyp1?0: comparator1 posi tive hysteresis control bits. 00: positive hysteresis disabled. 01: positive hysteresis = 5 mv. 10: positive hysteresis = 10 mv. 11: positive hysteresis = 20 mv. bits1?0: cp1hyn1?0: comparator1 nega tive hysteresis control bits. 00: negative hysteresis disabled. 01: negative hysteresis = 5 mv. 10: negative hysteresis = 10 mv. 11: negative hysteresis = 20 mv. r/w r r/w r/w r/w r/w r/w r/w reset value cp1en cp1out cp1rif cp1fif cp1hyp1 cp1hyp0 cp1hyn1 cp1hyn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9a
c8051f320/1 64 rev. 1.4 sfr definition 7.5. cpt1mx: comparator1 mux selection bits7?6: unused. read = 00b, write = don?t care. bits5?4: cmx1n1?cmx1n0: comparator1 negative input mux select. these bits select which port pin is us ed as the comparat or1 negative input. bits3?2: unused. read = 00b, write = don?t care. bits1?0: cmx1p1?cmx1p0: comparator1 positive input mux select. these bits select which port pin is used as the comparator1 positive input. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - cmx1n1 cmx1n0 - - cmx1p1 cmx1p0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9e cmx1n1 cmx1n0 negative input 00 p1.3 01 p1.7 10 p2.3 11 p2.7* cmx1p1 cmx1p0 positive input 00 p1.2 01 p1.6 10 p2.2 11 p2.6* *note: p2.6 and p2.7 available only on c8051f320 device s; selection reserved on c8051f321 devices.
rev. 1.4 65 c8051f320/1 sfr definition 7.6. cpt1md: comparator 1 mode selection bits7?6: unused. read = 00b, write = don?t care. bit5: cp1rie: comparator1 rising-edge interrupt enable. 0: comparator1 rising-edge interrupt disabled. 1: comparator1 rising-edge interrupt enabled. bit4: cp1fie: comparator1 fa lling-edge interrupt enable. 0: comparator1 falling-e dge interrup t disabled. 1: comparator1 falling-e dge interrup t enabled. bits3?2: unused. read = 00b. write = don?t care. bits1?0: cp1md1?cp1md0: comparator1 mode select. these bits select the response time for comparator1. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - cp1rie cp1fie - - cp1md1 cp1md0 00000010 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x9c mode cp1md1 cp1md0 cp1 response time (typ) 0 0 0 100 ns 1 0 1 175 ns 2 1 0 320 ns 3 1 1 1050 ns
c8051f320/1 66 rev. 1.4 table 7.1. comparator electrical characteristics v dd = 3.0 v, ?40 to +85 c unless otherwise noted. al l sp ecifications apply to bot h comparator0 and comparator1 unless otherwise noted. parameter conditions min typ max units response time: mode 0, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 100 ? ns cp0+ ? cp0? = ?100 mv ? 250 ? ns response time: mode 1, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 175 ? ns cp0+ ? cp0? = ?100 mv ? 500 ? ns response time: mode 2, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 320 ? ns cp0+ ? cp0? = ?100 mv ? 1100 ? ns response time: mode 3, vcm* = 1.5 v cp0+ ? cp0? = 100 mv ? 1050 ? ns cp0+ ? cp0? = ?100 mv ? 5200 ? ns common-mode rejection ratio ? 1.5 4 mv/v positive hysteresis 1 cp0hyp1?0 = 00 ? 0 1 mv positive hysteresis 2 cp0hyp1?0 = 01 2 5 10 mv positive hysteresis 3 cp0hyp1?0 = 10 7 10 20 mv positive hysteresis 4 cp0hyp1?0 = 11 15 20 30 mv negative hysteresis 1 cp0hyn1?0 = 00 0 1 mv negative hysteresis 2 cp0hyn1?0 = 01 2 5 10 mv negative hysteresis 3 cp0hyn1?0 = 10 7 10 20 mv negative hysteresis 4 cp0hyn1?0 = 11 15 20 30 mv inverting or non-inverting input v oltage range ?0.25 vdd + 0.25 v input capacitance ? 3 ? pf input bias current ? 0.001 ? na input offset voltage ?5 ? +5 mv power supply power supply rejection ? 0.1 ? mv/v power-up time ? 10 ? s supply current at dc mode 0 ? 7.6 20 a mode 1 ? 3.2 10 a mode 2 ? 1.3 5 a mode 3 ? 0.4 2.5 a *note: vcm is the common-mode voltage on cp0+ and cp0-.
rev. 1.4 67 c8051f320/1 8. voltage regulator (reg0) c8051f320/1 devices include a 5-to-3 v voltage regulator (reg0). when enabled, the reg0 output appe ars on the vdd pin and can be used to power ex ternal devices. reg0 can be enabled/disabled by software using bit regen in register reg0cn. see ta b l e 8.1 for reg0 electrical characteristics. note that the vbus signal must be connected to th e vbus pin wh en using the device in a usb network. the vbus signal should only be connected to the re gin pin when operating the device as a bus-powered function. reg0 configuration options are shown in figure 8.2 ? figure 8.5 . the input (vregin) and output (vdd) of the voltage regulator should both be protected by adding decou - pling and bypass capacitors on each pin to grou n d . suggested values for the two capacitors are 4.7 f + 0.1 f. these capacitors will in c r ease noise immunity and stabilize the voltage supply. v dd v dd reg0 4.7 f 4.7 f 0.1 f 0.1 f v regin figure 8.1. external capacitors for voltage regulator input/output 8.1. regulator mode selection reg0 offers a low power mode intended for use when the device is in suspend mode. in this low power mode, the reg0 output remains as specified; however the reg0 dynami c performance (response time) is degraded. see ta b l e 8.1 for normal and low power mode supply cu rr ent specificati ons. the reg0 mode selection is controlled via the regmod bit in regis ter reg0cn. 8.2. vbus detection when the usb function contro ller is used (see section section ?15. universal serial bus controller (usb)? on page 139 ), the vbus signal should be connected to the vbus pin. the vb stat bit (register reg0cn) indicates the current logic level of the vbus s i gnal. if enabled, a vbus interrupt will be gener - ated when the vbus signal matches the polarity selected by the vbpo l bit in register reg0cn. the vbus interrupt is leve l-sensitive, and has no asso ciated interrup t pending flag. the vbus interrupt will be active as long as the vbus signal matc hes the polarity selected by vbpol. see ta b l e 8.1 for vbus input parameters.
c8051f320/1 68 rev. 1.4 important note: when usb is selected as a reset source , a system reset will be generated when the vbus signal matches th e polarity selected by the vbpol bit. see section ?10. reset sources? on page 99 for details on selecting usb as a reset source. table 8.1. voltage regulator electrical specifications ?40 to +85 c unless otherwise specified. parameter conditions min typ max units input voltage range 1 2.7 ? 5.25 v output voltage (v dd ) 2 output current = 1 to 100 ma 3.0 3.3 3.6 v output current 2 ? ? 100 ma vbus detection input low voltage ? ? 1.0 v vbus detection input high voltage 3.0 ? ? v bias current normal mode (regmod = 0) low power mode (regmod = 1) ? 65 35 111 61 a dropout voltage (v do ) 3 ? 1 ? mv/ma notes: 1. input range specified for regulation. when an ex te rnal regulator is used, regin should be tied to v dd . 2. output current is total regulator output, including any current required by the c8051f320/1. 3. th e minimum input voltage is 2.70 v or vdd + v do (max load), whichever is greater. voltage regulator (reg0) 5v in 3v out vbus sense regin vbus from vbus to 3v power net device power net vdd c8051f320/1 figure 8.2. reg0 confi guration: usb bus-powered
voltage regulator (reg0) 5v in 3v out vbus sense regin vbus to 3v power net device power net vdd c8051f320/1 from 5v power net from vbus voltage regulator (reg0) 5v in 3v out vbus sense regin vbus from 3v power net device power net vdd c8051f320/1 from vbus rev. 1.4 69 c8051f320/1 figure 8.3. reg0 configuration: usb self-powered figure 8.4. reg0 conf iguration: usb self-pow ered, regulator disabled
c8051f320/1 70 rev. 1.4 figure 8.5. reg0 configur ation: no usb connection sfr definition 8.1. reg0cn: voltage regulator control voltage regulator (reg0) 5v in 3v out vbus sense regin vbus to 3v power net device power net vdd c8051f320/1 from 5v power net bit7: regdis: voltag e regulator disable. 0: voltage regulator enabled. 1: voltage regulator disabled. bit6: vbstat: vbus signal status. 0: vbus signal currently absent (device not attached to usb network). 1: vbus signal currently present (device attached to usb network). bit5: vbpol: vbus interr upt polarity select. this bit selects the vbus interrupt polarity. 0: vbus interrupt active when vbus is low. 1: vbus interrupt active when vbus is high. bit4: regmod: voltage re gulator mode select. this bit selects the voltage regulator mode. when regmod is set to ?1?, the voltage regu- lator operates in low power (suspend) mode. 0: usb0 voltage regulator in normal mode. 1: usb0 voltage regula tor in low power mode. bits3?0: reserved. read = 0000b. must write = 0000b. r/w r r/w r/w r/w r/w r/w r/w reset value regdis vbstat vbpol regmod reserved res erved reserved reserved 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc9
rev. 1.4 71 c8051f320/1 9. cip-51 microcontroller the mcu system controller core is the cip-51 microcon troller. the cip-51 is fully compatible with the mcs-51? instruction set; standard 803x/805x assemble rs and compilers can be used to develop soft - ware. the mcu family has a superset of all the peripherals included with a standard 8051. included are fou r 16-bit counter/timers (see description in section 19 ), an enhanced full-duplex uart (see description in section 17 ), an enhanced spi (see description in section 18 ), 256 bytes of internal ram, 128 byte spe - cial function register (sfr) address space ( section 9.2.6 ), and 25 port i/o (see description in section 14 ). the cip-51 also includes on-chip debug hardware (see description in section 21 ), and interfaces directly with the analog and digi t a l subsystems providing a complete data acquisition or control-system solution in a single integrated circuit. the cip-51 microcontroller core implements the standard 8051 organization and peripherals as well as additional c u stom peripherals and func tions to extend its capability (see figure 9.1 for a block diagram). the cip-51 includes the following features: - fully compatible wit h mcs-51 instruction set - 25 mips peak throughput with 25 mhz clock - 0 to 25 mhz clock frequency - 256 bytes of internal ram - 25 port i/o ('f320) / 21 port i/o ('f321) - extended interrupt handler - reset input - power management modes - on-chip debug logic - program and data memory security data bus tmp1 tmp2 prgm. address reg. pc incrementer alu psw data bus data bus memory interface mem_address d8 pipeline buffer data pointer interrupt interface system_irqs emulation_irq mem_control control logic a16 program counter (pc) stop clock reset idle power control register data bus sfr bus interface sfr_address sfr_control sfr_write_data sfr_read_data d8 d8 b register d8 d8 accumulator d8 d8 d8 d8 d8 d8 d8 d8 mem_write_data mem_read_data d8 sram address register sram (256 x 8) d8 stack pointer d8 figure 9.1. cip-51 block diagram
c8051f320/1 72 rev. 1.4 performance the cip-51 employs a pipelined architecture that grea tly increases its instruction throughput over the stan - dard 8051 architecture. in a standar d 8051, all inst ructions except for mul and div take 12 or 24 system clock cycles to execute, and usually have a maximum system clock of 12 mhz. by contrast, the cip-51 core exec ut es 70% of its instructions in one or tw o system clock cycles, with no instructions taking more than eight system clock cycles. with the cip-51's maximum system clock at 25 mhz, it has a peak throughput of 25 mips. the cip-51 has a to tal of 109 instructions. the table below shows the total number of instructions that for execution time. clocks to execute 1 2 2/3 3 3/4 4 4/5 5 8 number of instructions 26 50 5 14 7 3 1 2 1 programming and debugging support in-system programming of the flash program memory and communication with on-chip debug support logic is ac complished via the silicon labs 2-wire de velopment interface (c2). note that the re-program - mable flash can also be read and changed a single by te at a time by the application software using the movc and movx instructions. this feature allows program memory to be used for non-volatile data stor - age as well as updating program code under software control. the on-chip debug support logic facilit ates full speed in-circuit debugging, a llowing the setting of hardware breakpoints, starting, stopping and single stepping th rough program execution (including interrupt service routines), examination of the program's call stack, a nd reading/writing the conten ts of registers and mem - ory. this method of on-chip debugging is completely non-intrusive, requiring no ram, stack, timers, or ot he r on-chip resources. c2 details can be found in section ?21. c2 interface? on page 245 . the cip-51 is support ed by devel opment tools from silicon labs and third party vendors. silicon labs pro - vides an integrated development environment (ide) includ ing ed itor, macro assembler, debugger and pro - grammer. the ide's debugger and programmer interface to the cip-51 via the c2 interface to provide fast a nd e fficient in-system device programming and deb ugging. third party macro assemblers and c compil - ers are also available. 9.1. instruction set the instruction set of the cip-51 system controller is fully compatible with the standard mcs-51? instruc - tion set. standard 8051 development tools can be used to develop software for the cip-51. all cip-51 in str uctions are the binary and fu nctional equivalent of their mcs-51? counterparts, including opcodes, addressing modes and effect on psw flags. however, in struction timing is different than that of the stan - dard 8051. 9.1.1. instruction and cpu timing in many 8051 implementations, a distinction is ma de between machine cycles and clock cycles, with machine cycles varying from 2 to 12 clock cycles in length. however, the cip-51 implementation is based solely on clock cycle timing. all instructio n timings are specified in terms of clock cycles. due to the pipelined architecture of the cip-51, most in str uctions execute in the same number of clock cycles as there are program bytes in the instruction. conditional branch instruct ions take one less clock cycle to complete when the branch is not taken as opposed to when the branch is taken. table 9.1 is the cip-51 instruction set summary, which includes the mn emo nic, number of bytes, and number of clock cycles for each instruction.
rev. 1.4 73 c8051f320/1 9.1.2. movx instruction and program memory the movx instruction is typically used to access exte rnal data memory (note: the c8051f320/1 does not support off-chip data or program memory). in the cip-51, the movx write instru ction is used to accesses external ram (xram) and the on-chip program memo ry space implemented as re-programmable flash memory. the flash access feature provides a mechanism for the cip-51 to update program code and use the program memory space for non-volatile data storage. refer to section ?11. flash memory? on page 106 for further details. table 9.1. cip-51 instruction set summary mnemonic description bytes clock cycles arithmetic operations add a, rn add register to a 1 1 add a, direct add direct byte to a 2 2 add a, @ri add indirect ram to a 1 2 add a, #data add immediate to a 2 2 addc a, rn add register to a with carry 1 1 addc a, direct add direct byte to a with carry 2 2 addc a, @ri add indirect ram to a with carry 1 2 addc a, #data add immediate to a with carry 2 2 subb a, rn subtract register from a with borrow 1 1 subb a, direct subtract direct byte from a with borrow 2 2 subb a, @ri subtract indirect ram from a with borrow 1 2 subb a, #data subtract immediate from a with borrow 2 2 inc a increment a 1 1 inc rn increment register 1 1 inc direct increment direct byte 2 2 inc @ri increment indirect ram 1 2 dec a decrement a 1 1 dec rn decrement register 1 1 dec direct decrement direct byte 2 2 dec @ri decrement indirect ram 1 2 inc dptr increment data pointer 1 1 mul ab multiply a and b 1 4 div ab divide a by b 1 8 da a decimal adjust a 1 1 logical operations anl a, rn and register to a 1 1 anl a, direct and direct byte to a 2 2 anl a, @ri and indirect ram to a 1 2 anl a, #data and immediate to a 2 2 anl direct, a and a to direct byte 2 2 anl direct, #data and immediate to direct byte 3 3 orl a, rn or register to a 1 1 orl a, direct or direct byte to a 2 2 orl a, @ri or indirect ram to a 1 2 orl a, #data or immediate to a 2 2
c8051f320/1 74 rev. 1.4 orl direct, a or a to direct byte 2 2 orl direct, #data or immediate to direct byte 3 3 xrl a, rn exclusive-or register to a 1 1 xrl a, direct exclusive-or direct byte to a 2 2 xrl a, @ri exclusive-or indirect ram to a 1 2 xrl a, #data exclusive-or immediate to a 2 2 xrl direct, a exclusive-or a to direct byte 2 2 xrl direct, #data exclusive-or immediate to direct byte 3 3 clr a clear a 1 1 cpl a complement a 1 1 rl a rotate a left 1 1 rlc a rotate a left through carry 1 1 rr a rotate a right 1 1 rrc a rotate a right through carry 1 1 swap a swap nibbles of a 1 1 data transfer mov a, rn move register to a 1 1 mov a, direct move direct byte to a 2 2 mov a, @ri move indirect ram to a 1 2 mov a, #data move immediate to a 2 2 mov rn, a move a to register 1 1 mov rn, direct move direct byte to register 2 2 mov rn, #data move immediate to register 2 2 mov direct, a move a to direct byte 2 2 mov direct, rn move register to direct byte 2 2 mov direct, direct move direct byte to direct byte 3 3 mov direct, @ri move indirect ram to direct byte 2 2 mov direct, #data move immediate to direct byte 3 3 mov @ri, a move a to indirect ram 1 2 mov @ri, direct move direct byte to indirect ram 2 2 mov @ri, #data move immediate to indirect ram 2 2 mov dptr, #data16 load dptr with 16-bit constant 3 3 movc a, @a+dptr move code byte relative dptr to a 1 3 movc a, @a+pc move code byte relative pc to a 1 3 movx a, @ri move external data (8-bit address) to a 1 3 movx @ri, a move a to external data (8-bit address) 1 3 movx a, @dptr move external data (16-bit address) to a 1 3 movx @dptr, a move a to external data (16-bit address) 1 3 push direct push direct byte onto stack 2 2 pop direct pop direct byte from stack 2 2 xch a, rn exchange register with a 1 1 xch a, direct exchange direct byte with a 2 2 xch a, @ri exchange indirect ram with a 1 2 xchd a, @ri exchange low nibble of indirect ram with a 1 2 table 9.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
rev. 1.4 75 c8051f320/1 boolean manipulation clr c clear carry 1 1 clr bit clear direct bit 2 2 setb c set carry 1 1 setb bit set direct bit 2 2 cpl c complement carry 1 1 cpl bit complement direct bit 2 2 anl c, bit and direct bit to carry 2 2 anl c, /bit and complement of direct bit to carry 2 2 orl c, bit or direct bit to carry 2 2 orl c, /bit or complement of direct bit to carry 2 2 mov c, bit move direct bit to carry 2 2 mov bit, c move carry to direct bit 2 2 jc rel jump if carry is set 2 2/3 jnc rel jump if carry is not set 2 2/3 jb bit, rel jump if direct bit is set 3 3/4 jnb bit, rel jump if direct bit is not set 3 3/4 jbc bit, rel jump if direct bit is set and clear bit 3 3/4 program branching acall addr11 absolute subroutine call 2 3 lcall addr16 long subroutine call 3 4 ret return from subroutine 1 5 reti return from interrupt 1 5 ajmp addr11 absolute jump 2 3 ljmp addr16 long jump 3 4 sjmp rel short jump (relative address) 2 3 jmp @a+dptr jump indirect relative to dptr 1 3 jz rel jump if a equals zero 2 2/3 jnz rel jump if a does not equal zero 2 2/3 cjne a, direct, rel compare direct byte to a and jump if not equal 3 3/4 cjne a, #data, rel compare immediate to a and jump if not equal 3 3/4 cjne rn, #data, rel compare immediate to register and jump if not eq ual 3 3/4 cjne @ri, #data, rel compare immediate to indirect and jump if not eq ual 3 4/5 djnz rn, rel decrement register and jump if not zero 2 2/3 djnz direct, rel decrement direct byte and jump if not zero 3 3/4 nop no operation 1 1 table 9.1. cip-51 instructi on set summary (continued) mnemonic description bytes clock cycles
notes on registers, operands and addressing modes: rn - register r0-r7 of the currently selected register bank. @ri - data ram location address ed indirectly through r0 or r1. rel - 8-bit, signed (two?s complement) offset relative to the first byte of the following instruction. used by sjmp and all conditional jumps. direct - 8-bit internal data location?s address. this could be a direct-access data ram location (0x00- 0x7f) or an sfr (0x80-0xff). #data - 8-bit constant #data16 - 16-bit constant bit - direct-accessed bit in data ram or sfr addr11 - 11-bit destination address used by acall and ajmp. the destination mu st be within the same 2 kb page of program memory as the first byte of the following instruction. addr16 - 16-bit destination address used by lcall a nd ljmp. the destination may be anywhere within the 16 kb program memory space. there is one unused opcode (0xa5) that performs the same function as nop. all mnemonics copyrighted ? intel corporation 1980. c8051f320/1 76 rev. 1.4
rev. 1.4 77 c8051f320/1 9.2. memory organization the memory organization of the cip-51 system controller is similar to that of a standard 8051. there are two separate memory spaces: program memory and data memory. program and data memory share the same address space but are accessed via different in struction types. the cip-51 memory organization is shown in figure 9.2 . program/data memory (flash) (direct and indirect addressing) 0x00 0x7f upper 128 ram (indirect addressing only) 0x80 0xff special function register's (direct addressing only) data memory (ram) general purpose registers 0x1f 0x20 0x2f bit addressable lower 128 ram (direct and indirect addressing) 0x30 internal data address space external data address space xram - 1024 bytes (accessable using movx instruction) 0x0000 0x03ff same 2048 bytes as from 0x0000 to 0x07ff, wrapped on 2 kb boundaries 0x0400 0xffff 16 k flash (in-system programmable in 512 byte sectors) 0x0000 reserved 0x3e00 0x3dff usb fifos 1024 bytes 0x07ff 0x0800 figure 9.2. memory map 9.2.1. program memory the cip-51 core has a 64k-byte program memory spac e. the c8051f320/1 implements 16k bytes of this program memory space as in-system, re-programmabl e flash memory, organized in a contiguous block from addresses 0x0000 to 0x3fff. addresses above 0x3dff are reserved. program memory is normally assumed to be read-only . ho wever, the cip-51 can write to program memory by setting the program store write enable bit (psctl.0) and using the movx instru ction. this feature pro - vides a mechanism for the cip-51 to update program cod e and use the program memory space for non- volatile data storage. refer to section ?11. flash memory? on page 106 for further details.
c8051f320/1 78 rev. 1.4 9.2.2. data memory the cip-51 includes 256 of internal ram mapped in to the data memory space from 0x00 through 0xff. the lower 128 bytes of data memory are used for general purpose registers and scratch pad memory. eithe r direct or indirect addressing may be used to access the lower 128 bytes of data memory. locations 0 x00 through 0x1f are addressable as four banks of general purpose registers, each bank consisting of eight byte-wide registers. the next 16 bytes, locations 0x20 through 0x2f, may either be addressed as by tes or as 128 bit locations accessible with the direct addressing mode. the upper 128 bytes of data memory are accessible only by i ndir ect addressing. this region occupies the same address space as the special function regist ers (sfr) but is physically separate from the sfr space. the addressing mode used by an instruction when accessing locations above 0x7f determines whether the cpu accesses the upper 128 bytes of data memory space or th e sfrs. in structions that use direct addressing will access the sfr space. instructions using indirect addressing above 0x7f access the upper 128 bytes of data memory. figure 9.2 illustrates the data memory organization of the cip-51. 9.2.3. general purpose registers the lower 32 bytes of data memory, locations 0x00 through 0x1f, may be addressed as four banks of gen - eral-purpose registers. each bank consists of eigh t b yte-wide registers designated r0 through r7. only one of these banks may be enabled at a time. two bi ts in the program status word, rs0 (psw.3) and rs1 (psw.4), select the active register bank (see description of the psw in figure 9.4 ). this allows fast context switching when entering subroutines and interrupt serv ice ro utines. indirect addressing modes use regis - ters r0 and r1 as index registers. 9.2.4. bit addressable locations in addition to direct access to data memory organized as bytes, the sixteen data memory locations at 0x20 through 0x2f are also accessible as 128 individually addressable bits. each bit has a bit address from 0x 00 to 0x7f. bit 0 of the byte at 0x20 has bit address 0x00 while bit7 of the byte at 0x20 has bit address 0 x07. bit 7 of the byte at 0x2f has bit address 0x7f. a bit access is distinguished from a full byte access by the type of instruction used (bit source or destinat ion operands as opposed to a byte source or destina - tion). the mcs-51? assembly language allows an alternate no tation for bit addressing of the form xx.b where xx is the byte address and b is the bit position within the byte. for example, the instruction: mov c, 22h.3 moves the boolean value at 0x13 (bit 3 of the byte at location 0x22) into the carry flag. 9.2.5. stack a programmer's stack can be located anywhere in the 256-byte data memory. the stack area is desig - nated using the stack pointer (sp, 0x81) sfr. the sp will poin t to the last location used. the next value pushed on the stack is placed at sp +1 and then sp is incremented. a re set initializes the stack pointer to location 0x07. therefore, the first value pushed on the st ack is placed at location 0x08, which is also the first register (r0) of register bank 1. thus, if more than one register bank is to be used, the sp should be initialized to a location in the data memory not being used for data storage. the stack depth can extend up to 256 bytes.
rev. 1.4 79 c8051f320/1 9.2.6. special function registers the direct-access data memory locations from 0x80 to 0xff constitute the sp ecial function registers (sfrs). the sfrs provide control and data exchang e with the cip-51's resources and peripherals. the cip-51 duplicates the sfrs found in a typical 805 1 implementation as well as implementing additional sfrs used to configure and access the sub-systems uni que to the mcu. this allows the addition of new functionality while retain ing compatibility with the mc s-51? instruction set. ta b l e 9.2 list s the sfrs imple - me nted in the cip-51 system controller. the sfr registers are accessed anytime the direct ad dr essing mode is used to access memory locations from 0x80 to 0xff. sfrs with addresses ending in 0x 0 or 0x8 (e.g. p0, tcon, scon0, ie, etc.) are bit- addressable as well as byte-addressable. all other sfrs are byte-addressable only. unoccupied addresses in the sfr space are reserved for future use. accessing t hese areas will have an indeterminate effect and should be avoided. refer to the corres ponding pages of the datasheet, as indicated in ta b l e 9.3 , for a detailed description of each register. table 9.2. special function regist er (sfr) memory map f8 spi0cn pca0l pca0h pca0cpl0 pca0cph0 pca0cpl4 pca0cph4 vdm0cn f0 b p0mdin p1mdin p2mdin p3mdin eip1 eip2 e8 adc0cn pca0cpl1 pca0cph1 pca0cpl2 pca0cph2 pca0cpl3 pca0cph3 rstsrc e0 acc xbr0 xbr1 it01cf eie1 eie2 d8 pca0cn pca0md pca0cpm 0 pca0cpm 1 pca0cpm 2 d0 psw ref0cn c8 tmr2cn reg0cn tmr2rll tmr2rlh tmr2l tmr2h c0 smb0cn smb0cf smb0dat adc0gtl adc0gth adc0ltl adc0lth b8 ip clkmul amx0n amx0p adc0cf adc0l b0 p3 oscxcn oscicn oscicl flscl flkey a8 ie a0 p2 spi0cfg spi0ckr spi0dat p0mdout p1mdout p2mdout p3mdout 98 scon0 sbuf0 cpt1cn cpt0cn cpt1md cpt0md cpt1mx cpt0mx 90 p1 tmr3cn tmr3rll tmr3rlh tmr3l tmr3h usb0adr 88 tcon tmod tl0 tl1 th0 th1 ckcon psctl 80 p0 sp dpl dph pcon 0(8) 1(9) 2(a) 3(b) 4(c) 5(d) 6(e) 7(f) (bit addressable) pca0cpm 3 pca0cpm 4 p0skip p1skip p2skip usb0xcn adc0h clksel emi0cn usb0dat
c8051f320/1 80 rev. 1.4 table 9.3. special function registers sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page acc 0xe0 accumulator 86 adc0cf 0xbc adc0 configuration 48 adc0cn 0xe8 adc0 control 49 adc0gth 0xc4 adc0 greater-than compare high 50 adc0gtl 0xc3 adc0 greater-than compare low 50 adc0h 0xbe adc0 high 48 adc0l 0xbd adc0 low 48 adc0lth 0xc6 adc0 less-than compare word high 51 adc0ltl 0xc5 adc0 less-than compare word low 51 amx0n 0xba amux0 negative channel select 47 amx0p 0xbb amux0 positive channel select 46 b 0xf0 b register 86 ckcon 0x8e clock control 215 clksel 0xa9 clock select 124 clkmul 0xb9 clock multiplier control 122 cpt0cn 0x9b comparator0 control 60 cpt0md 0x9d comparator0 mode selection 62 cpt0mx 0x9f comparator0 mux selection 61 cpt1cn 0x9a comparator1 control 63 cpt1md 0x9c comparator1 mode selection 65 cpt1mx 0x9e comparator1 mux selection 64 dph 0x83 data pointer high 84 dpl 0x82 data pointer low 83 eie1 0xe6 extended interrupt enable 1 93 eie2 0xe7 extended interrupt enable 2 95 eip1 0xf6 extended interrupt priority 1 94 eip2 0xf7 extended interrupt priority 2 95 emi0cn 0xaa external memory interface control 115 flkey 0xb7 flash lock and key 112 flscl 0xb6 flash scale 113 ie 0xa8 interrupt enable 91 ip 0xb8 interrupt priority 92
rev. 1.4 81 c8051f320/1 it01cf 0xe4 int0/int1 configuration 96 oscicl 0xb3 internal oscillator calibration 118 oscicn 0xb2 internal oscillator control 118 oscxcn 0xb1 external oscillator control 121 p0 0x80 port 0 latch 133 p0mdin 0xf1 port 0 input mode configuration 133 p0mdout 0xa4 port 0 output mode configuration 133 p0skip 0xd4 port 0 skip 134 p1 0x90 port 1 latch 134 p1mdin 0xf2 port 1 input mode configuration 134 p1mdout 0xa5 port 1 output mode configuration 135 p1skip 0xd5 port 1 skip 135 p2 0xa0 port 2 latch 135 p2mdin 0xf3 port 2 input mode configuration 136 p2mdout 0xa6 port 2 output mode configuration 136 p2skip 0xd6 port 2 skip 136 p3 0xb0 port 3 latch 137 p3mdin 0xf4 port 3 input mode configuration 137 p3mdout 0xa7 port 3 output mode configuration 137 pca0cn 0xd8 pca control 240 pca0cph0 0xfc pca capture 0 high 244 pca0cph1 0xea pca capture 1 high 244 pca0cph2 0xec pca capture 2 high 244 pca0cph3 0xee pca capture 3high 244 pca0cph4 0xfe pca capture 4 high 244 pca0cpl0 0xfb pca capture 0 low 243 pca0cpl1 0xe9 pca capture 1 low 243 pca0cpl2 0xeb pca capture 2 low 243 pca0cpl3 0xed pca capture 3low 243 pca0cpl4 0xfd pca capture 4 low 243 pca0cpm0 0xda pca module 0 mode register 242 pca0cpm1 0xdb pca module 1 mode register 242 table 9.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page
c8051f320/1 82 rev. 1.4 pca0cpm2 0xdc pca module 2 mode register 242 pca0cpm3 0xdd pca module 3 mode register 242 pca0cpm4 0xde pca module 4 mode register 242 pca0h 0xfa pca counter high 243 pca0l 0xf9 pca counter low 243 pca0md 0xd9 pca mode 241 pcon 0x87 power control 98 psctl 0x8f program store r/w control 112 psw 0xd0 program status word 85 ref0cn 0xd1 voltage reference control 56 reg0cn 0xc9 voltage regulator control 70 rstsrc 0xef reset source configuration/status 104 sbuf0 0x99 uart0 data buffer 193 scon0 0x98 uart0 control 192 smb0cf 0xc1 smbus configuration 175 smb0cn 0xc0 smbus control 177 smb0dat 0xc2 smbus data 179 sp 0x81 stack pointer 84 spi0cfg 0xa1 spi configuration 203 spi0ckr 0xa2 spi clock ra te cont rol 205 spi0cn 0xf8 spi control 204 spi0dat 0xa3 spi data 205 tcon 0x88 timer/counter control 213 th0 0x8c timer/counter 0 high 216 th1 0x8d timer/counter 1 high 216 tl0 0x8a timer/counter 0 low 216 tl1 0x8b timer/counter 1 low 216 tmod 0x89 timer/counter mode 214 tmr2cn 0xc8 timer/counter 2 control 220 tmr2h 0xcd timer/counter 2 high 221 tmr2l 0xcc timer/counter 2 low 221 tmr2rlh 0xcb timer/counter 2 reload high 221 table 9.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page
rev. 1.4 83 c8051f320/1 9.2.7. register descriptions following are descriptions of sfrs related to the operati on of the cip-51 system controller. reserved bits should not be set to logic l. future product versions may use these bits to implement new features in which case the reset value of the bit will be logic 0, selecting the feature's default st ate. det ailed descriptions of the remaining sfrs are included in the sections of the datasheet associated with their corresponding sys - tem function. sfr definition 9.1. bits7?0: dpl: data pointer low. the dpl register is the low byte of the 16-bit dptr. dptr is used to access indirectly addressed memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x82 dpl: data pointer low byte tmr2rll 0xca timer/counter 2 reload low 221 tmr3cn 0x91 timer/counter 3control 225 tmr3h 0x95 timer/counter 3 high 226 tmr3l 0x94 timer/counter 3low 226 tmr3rlh 0x93 timer/counter 3 reload high 226 tmr3rll 0x92 timer/counter 3 reload low 226 usb0adr 0x96 usb0 indirect address register 143 usb0dat 0x97 usb0 data register 144 usb0xcn 0xd7 usb0 transceiver control 141 vdm0cn 0xff vdd monitor control 101 xbr0 0xe1 port i/o crossbar control 0 131 xbr1 0xe2 port i/o crossbar control 1 132 0x84?0x86, 0xab-0xaf, 0xb4, 0xb5, 0xbf , 0xc7, 0xce, 0xcf, 0xd2, 0xd3, 0xdf, 0xe3, 0xe5, 0xf5 reserved table 9.3. special functi on registers (continued) sfrs are listed in alphabetical order. all undefined sfr locations are reserved. register address description page
c8051f320/1 84 rev. 1.4 sfr definition 9.2. bits7?0: dph: data pointer high. the dph register is the high byte of the 16-bi t dptr. dptr is used to access indirectly addressed memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x83 dph: data pointer high byte sfr definition 9.3. bits7?0: sp: stack pointer. the stack pointer holds the location of the top of the stack. the stack pointer is incremented before every push operation. the sp register defaults to 0x07 after reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x81 sp: stack pointer
rev. 1.4 85 c8051f320/1 sfr definition 9.4. bit7: cy: carry flag. this bit is set when the last ar ithmetic operation resulted in a carry (addition) or a borrow (subtraction). it is cleared to logic 0 by all other arithmetic operations. bit6: ac: auxiliary carry flag this bit is set when the last arithmetic operation resulted in a carry into (addition) or a borrow from (subtraction) the high order nibble. it is cleared to logic 0 by all other arithmetic opera- tions. bit5: f0: user flag 0. this is a bit-addressable, general purpose flag for use under software control. bits4?3: rs1?rs0: register bank select. these bits select which register ba nk is used during register accesses. bit2: ov: overflow flag. this bit is set to 1 under the following circumstances: ? an add, addc, or subb instructi on causes a sign-change overflow. ? a mul instruction results in an overflow (result is greater than 255). ? a div instruction causes a divide-by-zero condition. the ov bit is cleared to 0 by the add, addc, subb, mul, and div inst ructions in all other cases. bit1: f1: user flag 1. this is a bit-addressable, general purpose flag for use under software control. bit0: parity: parity flag. this bit is set to logic 1 if the sum of the eight bits in the accumulator is odd and cleared if the sum is even. r/w r/w r/w r/w r/w r/w r/w r reset value cy ac f0 rs1 rs0 ov f1 parity 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd0 rs1 rs0 register bank address 0 0 0 0x00?0x07 0 1 1 0x08?0x0f 1 0 2 0x10?0x17 1 1 3 0x18?0x1f psw: program status word
c8051f320/1 86 rev. 1.4 sfr definition 9.5. bits7?0: acc: accumulator. this register is the accumulator for arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value acc.7 acc.6 acc.5 acc.4 acc.3 acc.2 acc.1 acc.0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xe0 acc: accumulator sfr definition 9.6. bits7?0: b: b register. this register serves as a second accumulator for certain arithmetic operations. r/w r/w r/w r/w r/w r/w r/w r/w reset value b.7b.6b.5b.4b.3b.2b.1b.000000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xf0 b: b register
rev. 1.4 87 c8051f320/1 9.3. interrupt handler the cip-51 includes an extended interrupt system supporting a total of 16 interrupt sources with two prior - ity levels. the allocation of inter rupt sources between on-chip periph erals and external inputs pins varies according to the specific version of the device. each interrupt source has one or more associated interrupt- pending flag(s) located in an sfr. when a peripheral or external source meets a valid interrupt condition, the associated interrupt-pend ing flag is set to logic 1. if interrupts are enabled for the source, an interrupt req uest is generated when the interrupt-pending flag is set. as soon as execution of the current instructio n is complete, the cpu generates an lcall to a prede - termined address to begin execution of an interrupt se rvice ro utine (isr). each isr must end with an reti instruction, which returns program execution to the next instruction that would have been executed if the interrupt request had not occurred. if interrupts are not enabled, the interrupt-pending flag is ignored by the hardware and program execution continues as normal . (the interrupt-pending flag is set to logic 1 regard - less of the interrupt's enable/disable state.) each interrupt source can be individually enabled or di sabled through the use of an associated interrupt enable bit in an sfr (ie-eie2). ho wever, interrupts must first be globally enabled by setting the ea bit (ie.7) to logic 1 before the individual interrupt enables are re cogn ized. setting the ea bit to logic 0 disables all interrupt sources regardless of the individual interrupt-enable settings. note : an y instruction which clears the ea bit should be immediately followed by an instruction which has two or more opcode bytes. for example: // in 'c': ? ea = 0; // clear ea bit ? ea = 0; // ... followed by another 2-byte opcode ; in assembly: clr ea ; clear ea bit ? clr ea ; ... followed by another 2-byte opcode if an interrupt is posted during the execution phase of a "clr ea" opcode (or an y instruction which clears the ea bit), and the instruction is followed by a single-c ycle instruction, the interrupt may be taken. if the ea bit is read inside the interrupt service routine, it will return a '0'. when the "clr ea" opcode is followed by a multi-cycle instruction, the interrupt will not be taken. some interrupt-pending flags are automatically cleare d by the hardware when the cpu vectors to the isr. however, most are not cleared by the hardware and must be cleared by software before returning from the isr. if an interrupt-pending flag remains set after the cpu completes the return-from-interrupt (reti) instruction, a new interr upt request will be gen erated immediately and the cpu will re-enter the isr after the completion of th e next instruction. 9.3.1. mcu interrupt sources and vectors the mcu supports 16 interrupt sources. software can simulate an interrupt by setting any interrupt-pend - ing flag to logic 1. if interrupts are enab led for the flag, an in terrupt reque st will be generat ed and the cpu will vector to the isr address associated with the interrup t-pending flag. mcu inte rrupt sources, associ - ated vector addresses, priority order and control bits are summarized in ta b l e 9.4 on page 89 . refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt co nditions for the peripheral and the behavior of its interrupt-pending flag(s).
c8051f320/1 88 rev. 1.4 9.3.2. external interrupts the /int0 and /int1 external interrupt sources are configurable as active high or low, edge or level sensi - tive. the in0pl (/int0 polarity) and in1pl (/int1 polarity ) bit s in the it01cf register select active high or active low; the it0 and it1 bits in tcon ( section ?19.1. timer 0 and timer 1? on page 209 ) select level or edge sensitive. the table below lis t s the possible configurations. active low, edge sensitive active low, edge sensitive active high, edge sensitive active high, edge sensi - tive active low, level sensitive active low, level sensitive active high, level sensitive active high, level sensitive /int0 and /int1 are assigned to port pins as defined in the it01cf register (see figure 9.13 ). note that /int0 and /int0 port pin assignment s are independent of any cros sbar assignments. /int0 and /int1 will monitor their assigned port pins without disturbing t he peripheral that was assigned the port pin via the crossbar. to assign a port pin only to /int0 and/or /i nt1, configure the crossbar to skip the selected pin(s). this is accomplished by setting th e associated bit in register xbr0 (see section ?14.1. priority crossbar decoder? on page 128 for complete details on configuring the crossbar). ie0 (tcon.1) and ie1 (tcon.3) serve as the interr upt- pen ding flags for the /int0 and /int1 external interrupts, respectively. if an /int0 or /int1 external interrupt is configured as edge-sensitive, the corre - sponding interrupt-pending flag is automatically clear ed by th e hardware when the cpu vectors to the isr. when configured as level sensitive, the interrupt-pendi ng flag remains logic 1 while the input is active as defined by the corresponding polarity bit (in0pl or in 1pl); the flag remains logi c 0 while the input is inac - tive. the external interrupt source must hold the input a c tive until the interrupt request is recognized. it must then deactivate the interrup t request before execution of the isr completes or another interrupt request will be generated. 9.3.3. interrupt priorities each interrupt source can be individually programmed to one of two priority levels: low or high. a low prior - ity interrupt service routine can be pree mpted b y a high priority interrupt. a high priority interrupt cannot be preempted. each interrupt has an associated interrupt priority bit in an sfr (ip or eip2) used to configure its priority level. low priority is th e default. if two interrupts are recognized simultaneously, the interrupt with the higher priority is serviced first. if both interrupts have the same priority level, a fixed priority order is used to arbitrate, given in ta b l e 9.4 . it0 in0pl /int0 interrupt it1 in1pl /int1 interrupt 10 10 11 11 00 00 01 01
rev. 1.4 89 c8051f320/1 9.3.4. interrupt latency interrupt response time depends on the state of the cpu when the interrupt occurs. pending interrupts are sampled and priority decoded each sys tem clock cycle. therefore, the fa stest possible response time is 5 system clock cycles: 1 clock cycle to detect the interrupt and 4 clock cycles to complete the lcall to the isr. if an interrupt is pending when a reti is execut ed, a single instruction is executed before an lcall is made to service the pending interrupt. therefore, the maximum response time for an interrupt (when no other interrupt is currently being serviced or the new in terrupt is of greater priority) occurs when the cpu is performing an reti instruct ion followed by a div as the next instructio n. in this case, th e response time is 18 system clock cycles: 1 clock cycle to detect the interrupt, 5 clock cycles to execute the reti, 8 clock cyc les to complete the div instruction and 4 clock cycles to execute the lcall to the isr. if the cpu is ex ecuting an isr for an interr upt with equal or higher pr iority, the new interrupt will not be serviced until the current isr completes, including the reti and following instruction. note that the cpu is stalled du rin g flash write/erase operations and usb fifo movx accesses (see sec - tion ?12.2. accessing usb fifo space? on page 114 ). interrupt servic e latency will be increased for inter - rupts occuring while the cpu is stall ed. the latency for these situations will be determined by the standard interrupt service procedure (as described above ) and the amount of time the cpu is stalled. table 9.4. interrupt summary interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control reset 0x0000 to p none n/a n/a always enabled always highe st external interrupt 0 (/ int0) 0x0003 0 ie0 (tcon.1) y y ex0 (ie.0) px0 (ip .0) timer 0 overflow 0x000b 1 tf0 (tcon.5) y y et0 (ie.1) pt0 (ip.1) external interrupt 1 (/ int1) 0x0013 2 ie1 (tcon.3) y y ex1 (ie.2) px1 (ip .2) timer 1 overflow 0x001b 3 tf1 (tcon.7) y y et1 (ie.3) pt1 (ip.3) uart0 0x0023 4 ri0 (scon0.0) ti0 (scon0.1) y n es0 (ie.4) ps0 (ip .4) timer 2 overflow 0x002b 5 tf2h (tmr2cn.7) tf2l (tmr2cn.6) y n et2 (ie.5) pt2 (ip.5) spi0 0x0033 6 spif (spi0cn.7) ? wcol (s pi0cn.6) modf (spi0cn.5) rxovrn (s pi0cn.4) y n espi0 (ie.6) pspi0 (ip .6) smb0 0x003b 7 si (smb0cn.0) y n esmb0 (eie1.0) psmb0 (eip1.0) usb0 0x0043 8 special n n eusb0 (eie1.1) pusb0 (eip1.1) adc0 window comp are 0x004b 9 ad0wint (a dc0cn.3) y n ewadc0 (eie1.2) pwadc0 (eip1.2)
c8051f320/1 90 rev. 1.4 9.3.5. interrupt register descriptions the sfrs used to enable the interrupt sources and set t heir priority level are described below. refer to the datasheet section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the peripheral and the behavior of its interrupt-pending flag(s). adc0 conversion complete 0x0053 10 ad0int (adc0cn.5) y n eadc0 (eie1.3) padc0 (eip1.3) programmable counter array 0x005b 11 cf (pca0cn.7) ccfn (pca0cn.n) y n epca0 (eie1.4) ppca0 (eip1.4) comparator0 0x0063 12 cp0fif (cpt0cn.4) cp0rif (cpt0cn.5) n n ecp0 (eie1.5) pcp0 (eip1.5) comparator1 0x006b 13 cp1fif (cpt1cn.4) cp1rif (cpt1cn.5) n n ecp1 (eie1.6) pcp1 (eip1.6) timer 3 overflow 0x0073 14 tf3h (tmr3cn.7) tf3l (tmr3cn.6) n n et3 (eie1.7) pt3 (eip1.7) vbus level 0x007b 15 n/a n/a n/a evbus (eie2.0) pvbus (eip2.0) table 9.4. interrupt summary (continued) interrupt source interrupt vector priority order pending flag bit addressable? cleared by hw? enable flag priority control
rev. 1.4 91 c8051f320/1 sfr definition 9.7. bit7: ea: enable all interrupts. this bit globally enables/disable s all interrupts. it ov errides the individual interrupt mask set- tings. 0: disable all interrupt sources. 1: enable each interrupt according to its individual mask setting. bit6: espi0: enable serial periph eral interface ( spi0) interrupt. this bit sets the masking of the spi0 interrupts. 0: disable all spi0 interrupts. 1: enable interrupt requests generated by spi0. bit5: et2: enable timer 2 interrupt. this bit sets the masking of the timer 2 interrupt. 0: disable timer 2 interrupt. 1: enable interrupt requests generated by the tf2l or tf2h flags. bit4: es0: enable uart0 interrupt. this bit sets the masking of the uart0 interrupt. 0: disable uart0 interrupt. 1: enable uart0 interrupt. bit3: et1: enable timer 1 interrupt. this bit sets the masking of the timer 1 interrupt. 0: disable all timer 1 interrupt. 1: enable interrupt requests generated by the tf1 flag. bit2: ex1: enable exte rnal interrupt 1. this bit sets the masking of external interrupt 1. 0: disable external interrupt 1. 1: enable interrupt requests generated by the /int1 input. bit1: et0: enable timer 0 interrupt. this bit sets the masking of the timer 0 interrupt. 0: disable all timer 0 interrupt. 1: enable interrupt requests generated by the tf0 flag. bit0: ex0: enable exte rnal interrupt 0. this bit sets the masking of external interrupt 0. 0: disable external interrupt 0. 1: enable interrupt requests generated by the /int0 input. r/w r/w r/w r/w r/w r/w r/w r/w reset value ea espi0 et2 es0 et1 ex1 et0 ex0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa8 ie: interrupt enable
c8051f320/1 92 rev. 1.4 sfr definition 9.8. bit7: unused. read = 1b, write = don't care. bit6: pspi0: serial peripheral interfac e (spi0) interrupt priority control. this bit sets the priority of the spi0 interrupt. 0: spi0 interrupt set to low priority level. 1: spi0 interrupt set to high priority level. bit5: pt2: timer 2 interrupt priority control. this bit sets the priority of the timer 2 interrupt. 0: timer 2 interrupt set to low priority level. 1: timer 2 interrupts set to high priority level. bit4: ps0: uart0 interrupt priority control. this bit sets the priority of the uart0 interrupt. 0: uart0 interrupt set to low priority level. 1: uart0 interrupts set to high priority level. bit3: pt1: timer 1 interrupt priority control. this bit sets the priority of the timer 1 interrupt. 0: timer 1 interrupt set to low priority level. 1: timer 1 interrupts set to high priority level. bit2: px1: external interrupt 1 priority control. this bit sets the priority of th e external interr upt 1 interrupt. 0: external interrupt 1 set to low priority level. 1: external interrupt 1 set to high priority level. bit1: pt0: timer 0 interrupt priority control. this bit sets the priority of the timer 0 interrupt. 0: timer 0 interrupt set to low priority level. 1: timer 0 interrupt set to high priority level. bit0: px0: external interrupt 0 priority control. this bit sets the priority of th e external interr upt 0 interrupt. 0: external interrupt 0 set to low priority level. 1: external interrupt 0 set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - pspi0 pt2 ps0 pt1 px1 pt0 px0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb8 ip: interrupt priority
rev. 1.4 93 c8051f320/1 sfr definition 9.9. bit7: et3: enable timer 3 interrupt. this bit sets the masking of the timer 3 interrupt. 0: disable timer 3 interrupts. 1: enable interrupt requests generated by the tf3l or tf3h flags. bit6: ecp1: enable comparator1 (cp1) interrupt. this bit sets the masking of the cp1 interrupt. 0: disable cp1 interrupts. 1: enable interrupt requests generated by the cp1rif or cp1fif flags. bit5: ecp0: enable comparator0 (cp0) interrupt. this bit sets the masking of the cp0 interrupt. 0: disable cp0 interrupts. 1: enable interrupt requests generated by the cp0rif or cp0fif flags. bit4: epca0: enable pr ogrammable counter array (pca0) interrupt. this bit sets the masking of the pca0 interrupts. 0: disable all pca0 interrupts. 1: enable interrupt requests generated by pca0. bit3: eadc0: enable adc0 conv ersion complete interrupt. this bit sets the masking of the ad c0 conversion co mplete interrupt. 0: disable adc0 conversion complete interrupt. 1: enable interrupt requests generated by the ad0int flag. bit2: ewadc0: enable window comparison adc0 interrupt. this bit sets the masking of adc0 window comparison interrupt. 0: disable adc0 window comparison interrupt. 1: enable interrupt requests generated by adc0 window compare flag (ad0wint). bit1: eusb0: enable usb0 interrupt. this bit sets the masking of the usb0 interrupt. 0: disable all usb0 interrupts. 1: enable interrupt requests generated by usb0. bit0: esmb0: enable smbu s (smb0) interrupt. this bit sets the masking of the smb0 interrupt. 0: disable all smb0 interrupts. 1: enable interrupt requests generated by smb0. r/w r/w r/w r/w r/w r/w r/w r/w reset value et3 ecp1 ecp0 epca0 eadc0 ewadc0 eusb0 esmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe6 eie1: extended interrupt enable 1
c8051f320/1 94 rev. 1.4 sfr definition 9.10. bit7: pt3: timer 3 interr upt priority control. this bit sets the priority of the timer 3 interrupt. 0: timer 3 interrupts set to low priority level. 1: timer 3 interrupts set to high priority level. bit6: pcp1: comparator1 (cp1) interrupt priority control. this bit sets the priori ty of the cp1 interrupt. 0: cp1 interrupt set to low priority level. 1: cp1 interrupt set to high priority level. bit5: pcp0: comparator0 (cp0) interrupt priority control. this bit sets the priori ty of the cp0 interrupt. 0: cp0 interrupt set to low priority level. 1: cp0 interrupt set to high priority level. bit4: ppca0: programmable counter array (pca0) interrupt priority control. this bit sets the priority of the pca0 interrupt. 0: pca0 interrupt set to low priority level. 1: pca0 interrupt set to high priority level. bit3: padc0 adc0 conversion comp lete interrupt pr iority control. this bit sets the priority of the adc0 conversion complete interrupt. 0: adc0 conversion complete inte rrupt set to low priority level. 1: adc0 conversion complete inte rrupt set to high priority level. bit2: pwadc0: adc0 window compar ator interrupt pr iority control. this bit sets the priority of the adc0 window interrupt. 0: adc0 window interrupt set to low priority level. 1: adc0 window interrupt set to high priority level. bit1: pusb0: usb0 interr upt priority control. this bit sets the priority of the usb0 interrupt. 0: usb0 interrupt set to low priority level. 1: usb0 interrupt set to high priority level. bit0: psmb0: smbus (smb0) in terrupt priority control. this bit sets the priority of the smb0 interrupt. 0: smb0 interrupt set to low priority level. 1: smb0 interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value pt3 pcp1 pcp0 ppca0 padc0 pwadc0 pusb0 psmb0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf6 eip1: extended interrupt priority 1
rev. 1.4 95 c8051f320/1 sfr definition 9.11. bits7?1: unused. read = 0000000b. write = don?t care. bit0: evbus: enable vbus level interrupt. this bit sets the masking of the vbus interrupt. 0: disable all vbus interrupts. 1: enable interrupt requests generated by vbus level sense. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - - - evbus 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe7 eie2: extended interrupt enable 2 sfr definition 9.12. bits7?1: unused. read = 0000000b. write = don?t care. bit0: pvbus: vbus level inte rrupt priority control. this bit sets the priority of the vbus interrupt. 0: vbus interrupt set to low priority level. 1: vbus interrupt set to high priority level. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - - - pvbus 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf7 eip2: extended interrupt priority 2
c8051f320/1 96 rev. 1.4 sfr definition 9.13. bit7: in1pl: /int1 polarity 0: /int1 input is active low. 1: /int1 input is active high. bits6?4: in1sl2?0: /int1 port pin selection bits these bits select which port pin is assigned to /int1. note that this pin assignment is inde- pendent of the crossbar; /int1 will monitor th e assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). bit3: in0pl: /int0 polarity 0: /int0 interrupt is active low. 1: /int0 interrupt is active high. bits2?0: int0sl2?0: /int0 port pin selection bits these bits select which port pin is assigned to /int0. note that this pin assignment is inde- pendent of the crossbar. /int 0 will monitor the assigned port pin without disturbing the peripheral that has been assigned the port pin via the crossbar. the crossbar will not assign the port pin to a peripheral if it is c onfigured to skip the selected pin (accomplished by setting to ?1? the corresponding bit in register p0skip). r/w r/w r/w r/w r/w r/w r/w r/w reset value in1pl in1sl2 in1sl1 in1sl0 in0pl in0sl2 in0sl1 in0sl0 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe4 note: refer to figure 19.1 for int0/1 ed ge- or level-sensitiv e interrupt selection. in1sl2-0 /int1 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 in0sl2-0 /int0 port pin 000 p0.0 001 p0.1 010 p0.2 011 p0.3 100 p0.4 101 p0.5 110 p0.6 111 p0.7 it01cf: int0/int 1 configuration
rev. 1.4 97 c8051f320/1 9.4. power management modes the cip-51 core has two software programmable power management modes: idle and stop. idle mode halts the cpu while leaving the peripherals and clocks active. in stop mode, the cpu is halted, all inter - rupts, are inactive, and the internal oscillator is st opped (analog pe ripherals remain in th eir selected states; the external oscillator is not affected). since clocks are running in idle mode, power consumption is depen - dent upon the system clock frequency and the number of p eripherals left in active mode before entering idle. stop mode consumes the least power. figure 1.15 describes the power control register (pcon) used to control the cip-51's power management modes. although the cip-51 has idle and stop modes built in ( as with any standard 8051 architecture), power management of the entire mcu is better accomplished through system clock and individual peripheral management. each analog peripheral can be disabled when not in use and placed in low power mode. digital peripherals, such as timers or serial buses, draw little power when they are not in use. turning off the oscillators lowers power consum ption considerably; however a reset is required to restart the mcu. the internal oscillator can be placed in suspend mode (s ee section ?13. oscillators? on page 116 ). in sus - pend mode, the intern al oscillator is s topped until a non-idle u sb event is detected, or the vbus input sig - nal matches the polarity selected by the vbpol bit in r egister reg0cn ( figure 8.1 on page 70 ). 9.4.1. idle mode setting the idle mode select bit (pcon.0) causes the cip-51 to halt the cpu and enter idle mode as soon as the instruction that sets the bit completes executio n. all internal registers and memory maintain their original data. all analog and digital peripherals can remain active during idle mode. idle mode is terminated when an enabled interrupt is asserted or a reset occurs. the assertion of an enabled interrupt will cause the idle mode selection bit (pcon.0) to be cleared and the cpu to resume operation. the pen ding interrupt will be serviced and the next in struction to be executed after the return from interrupt (reti) will be the instruction immedi ately following the one that se t the idle mode select bit. if idle mode is terminated by an internal or external reset, the cip-51 performs a normal reset sequence and begins program execution at address 0x0000. if enabled, the watchdog timer (wdt) will eventually cause an internal watchdog reset and thereby termi - nate the idle mode. this feature protects the system from an unintended permanent shutdown in the event o f an inadvertent write to the pcon register. if this behavior is not desired, th e wdt may be disabled by software prior to entering the idle mo de if the wdt was initially configured to allow this operation. this pro - vides the opportunity for additional power savings, allo w ing the system to remain in the idle mode indefi - nitely, waiting for an external stimulus to wake up the system. refer to section ?10.6. pca watchdog timer reset? on page 102 for more information on the use and configuration of the wdt. 9.4.2. stop mode setting the stop mode select bit (pcon.1) causes the ci p-51 to enter stop mode as soon as the instruc - tion that sets the bit comp letes execution. in s top mo de the internal oscillator, cpu, and all digital peripher - als are stopped; the st ate of the external oscillator circuit is not affected. each analog peripheral (including the external oscillator circuit) may be shut down individually prior to entering stop mo de. stop mode can only be terminated by an internal or external reset. on reset, the cip-51 performs the normal reset sequence and begins program execution at address 0x0000. if enabled, the missing clock detect or will cause an internal reset and ther eby terminate th e stop mode. the missing clock detector should be disabled if the cpu is to be put to in stop mode for longer than the mcd timeout of 100 sec.
c8051f320/1 98 rev. 1.4 sfr definition 9.14. bits7?2: gf5?gf0: general purpose flags 5?0. these are general purpose flags for use under software control. bit1: stop: stop mode select. setting this bit will place the cip-51 in stop m ode. this bit will always be read as 0. 1: cpu goes into stop mode (internal oscillator stopped). bit0: idle: idle mode select. setting this bit will place the cip-51 in idle m ode. this bit will always be read as 0. 1: cpu goes into idle mode. (shuts off clock to cpu, but clock to timers, interrupts, serial ports, and analog peri pherals are still active.) r/w r/w r/w r/w r/w r/w r/w r/w reset value gf5 gf4 gf3 gf2 gf1 gf0 stop idle 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x87 pcon: power control
rev. 1.4 99 c8051f320/1 10. reset sources reset circuitry allows the controller to be easily placed in a predefined default condition. on entry to this reset state, th e following occur: ? cip-51 halts program execution ? special function registers (sfrs) are initialized to their defined reset values ? external port pins are forced to a known state ? interrupts and timers are disabled. all sfrs are reset to the predefined values noted in the sfr detailed descriptions. the contents of internal d a ta memory are unaffected during a reset; any prev iously stored data is preserved. however, since the stack pointer sfr is reset, the stack is effectively lo st even though the data on the stack is not altered. the port i/o latches are reset to 0xff (all logic ones ) in o pen-drain mode. weak pull-ups are enabled dur - ing and after the reset. for vdd monitor and power-on resets, the /rst pin is driven low until the device e x its the reset state. on exit from the reset state, the program counter (pc) is re set, and the system clock defaults to the inter - nal oscillator. refer to section ?13. oscillators? on page 116 for information on selecting and configuring the system clock source. the watchdog timer is enabled with the system clock divide d by 12 as its clock source ( section ?20.3. watchdog timer mode? on page 236 details the use of the watchdog timer). pro - gram execution begins at location 0x0000. pca wdt missing clock detector (one- shot) software reset (swrsf) system reset reset funnel px.x px.x en system clock cip-51 microcontroller core extended interrupt handler clock select en wdt enable mcd enable errant flash operation + - comparator 0 c0rsef /rst (wired-or) power on reset + - vdd supply monitor enable '0' internal oscillator xtal1 xtal2 external oscillator drive clock multiplier usb controller vbus transition enable figure 10.1. reset sources
c8051f320/1 100 rev. 1.4 10.1. power-on reset during power-up, the device is held in a reset state and the /rst pin is driven low until vdd settles above v rst . a power-on reset delay (t pordelay ) occurs before the device is released from reset; this delay is typically less than 0.3 ms. figure 10.2 . plots the power-on and vdd monitor reset timing. on exit from a power-on reset, the porsf flag (rstsrc.1) is set by hardware to logic 1. when porsf is set, all of the other reset flags in the rstsrc regist er are indeterminate (porsf is cleared by all other resets). since all resets cause program execution to begin at the same location (0x0000) software can read the porsf flag to determine if a power-up was t he cause of reset. the content of internal data mem - ory should be assumed to be undefined after a power-on reset. the vdd monitor is enabled following a po we r-on reset. software can force a power-on reset by writin g ?1? to the pinrs f bit in register rstsrc. power-on reset vdd monitor reset /rst t volts 1.0 2.0 logic high logic low t pordelay v d d 2.70 2.4 v rst vdd figure 10.2. power-on a nd vdd monitor reset timing
rev. 1.4 101 c8051f320/1 10.2. power-fail r eset / vdd monitor when a power-down transition or power irregularity causes vdd to drop below v rst , the power supply monitor will drive the /rst pin low and ho ld the cip-51 in a reset state (see figure 10.2 ). when vdd returns to a level above v rst , the cip-51 will be released from the reset state. note that even though inter - nal data memory contents are not altered by the power -fail reset, i t is impossible to determine if vdd dropped below the level required for data retention. if the porsf flag reads ?1?, the data may no longer be valid. the vdd monitor is enabled after power-on resets; however its defined state (enabled/disabled) is not altered by any other reset source. for example, if the vdd monitor is enabled and a software reset is performed, the vdd monitor will st ill be enabled after the reset. important note: t he vdd monitor must be enabled before it is selected as a reset source. selecting the vdd monitor as a reset source before it is enabled and stabilized will cause a system reset. the procedure for configuring the vdd monitor as a reset source is shown below: step 1. enable the vdd monitor (vdm0cn.7 = ?1?). s t ep 2. wait for the vdd monitor to stabilize (s ee table 10.1 for the vdd monitor turn-on time). step 3. select the vdd monitor as a reset source (rstsrc.1 = ?1?). see figure 10.2 for vdd monitor timing. see ta b l e 10.1 for complete electrical characteristics of the vdd monitor. sfr definition 10.1. bit7: vdmen: vdd monitor enable. this bit turns the vdd monitor circuit on/off. the vdd monitor cannot generate system resets until it is also select ed as a reset source in register rstsrc (figure 10.2). the vdd monitor must be allowed to stabilize befo re it is selected as a reset source. selecting the vdd monitor as a reset source before it has stabilized will ge nerate a system reset. see table 10.1 for the minimum vdd monitor turn-on time. the vdd monitor is enabled fol- lowing all por resets. 0: vdd monitor disabled. 1: vdd monitor enabled. bit6: vddstat: vdd status. this bit indicates the current power supply status (vdd monitor output). 0: vdd is at or below the vdd monitor threshold. 1: vdd is above the vdd monitor threshold. bits5?0: reserved. read = variable. write = don?t care. r / wrrrrrrrr e s e t v a l u e vdmen vddstat reserved reserved reserved reserved reserved reserved variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xff vdm0cn: vdd monitor control
c8051f320/1 102 rev. 1.4 10.3. external reset the external /rst pin provides a means for external ci rcuitry to force the device into a reset state. assert - ing an active-low signal on the /rst pin generates a reset; an external pull-up and/or decoupling of the /rst pin may be necessary to avoid erroneous noise-induced resets. see ta b l e 10.1 for complete /rst pin specifications. the pinrsf flag (rstsrc.0) is set on exit from an external reset. 10.4. missing clock detector reset the missing clock detector (mcd) is a on e-shot circuit that is triggered by the system clock. if more than 100 s pass between rising edges on the system clock, the one-shot will time ou t and generat e a reset. after a mcd reset, the mcdrsf flag (rstsrc.2) will read ?1?, signifying the mcd as the reset source; otherwise, this bit reads ?0?. writ ing a ?1? to the mcdrsf bit enables the missing clock detector; writing a ?0? disables it. the state of the /rst pin is unaffected by this reset. 10.5. comparator0 reset comparator0 can be configured as a reset source by writing a ?1? to the c0rsef flag (rstsrc.5). comparator0 should be enabled and allowed to settle prior to writing to c0rsef to prevent any turn-on chatter on the output from generating an unwanted rese t. the comparator0 reset is active-low: if the non- inverting input voltage (on cp0+) is less than the in verting input voltage (on cp0-), a system reset is gen - erated. after a compar ator0 reset, the c0rsef flag (rstsrc.5) will read ?1? signifying comparator0 as the reset source; otherwise, this bit reads ?0?. the state of the /rst pin is unaffected by this reset. note : when comparator0 is not enabled but is enabled as a reset sour ce, a reset will no t be g enerated. 10.6. pca watchdog timer reset the programmable watchdog timer (wdt) function of the programmable counter array (pca) can be used to prevent software from running out of cont rol during a system malfunction. the pca wdt function can be enabled or disabled by software as described in section ?20.3. watchdog timer mode? on page 236 ; the wdt is enabled and clocked by sysclk / 12 following any reset. if a system malfunction prevents user software from updating the wdt, a re set is gen erated and the wdtrsf bit (rstsrc.5) is set to ?1?. the state of the /rst pin is unaffected by this reset. 10.7. flash error reset if a flash read/write/era se or program read targets an illegal address, a system reset is generated. this may occur due to any of the following: ? a flash write or erase is attempted above user code space. this occurs when pswe is set to ?1? and a movx write operation is attempted above address 0x3dff. ? a flash read is attempted above user code space. th is occurs when a movc operation is attempted above address 0x3dff. ? a program read is attempted above user code spac e. this occu rs when user code attempts to branch to an address above 0x3dff. ? a flash read, write or erase attempt is re stricted d ue to a flash security setting (see section ?11.3. security options? on page 108 ). the ferror bit (rstsrc.6) is set following a flash erro r re set. the state of the /rst pin is unaffected by this reset.
rev. 1.4 103 c8051f320/1 10.8. software reset software may force a reset by writing a ?1? to the swrsf bit (rstsrc.4). the swrsf bit will read ?1? fol - lowing a software forced reset. the state of th e /rst pin is unaffected by this reset. 10.9. usb reset writing ?1? to the usbrsf bit in register rstsrc sele cts usb0 as a reset source . with usb0 selected as a reset source, a system reset will be generated when either of the following occur: 1. reset signaling is detected on the usb network. the usb func tion controller (usb0) must be enabled for reset signa ling to be detected. see section ?15. universal serial bus con - troller (usb)? on page 139 for information on the usb function controller. 2. the voltage on the vbus pin matches the po larity selected by the vbpol bit in register reg0cn. see section ?8. voltage regulator (reg0)? on page 67 for details on the vbus detection circuit. the usbrsf bit will read ?1? following a usb reset. the st ate of the /rst pin is unaffected by this reset.
c8051f320/1 104 rev. 1.4 sfr definition 10.2. bit7: usbrsf: usb reset flag 0: read: last reset was not a usb reset; write: usb resets disabled. 1: read: last reset was a usb reset; write: usb resets enabled. bit6: ferror: flash error indicator. 0: source of last reset was not a flash read/write/erase error. 1: source of last reset was a flash read/write/erase error. bit5: c0rsef: comparator0 reset enable and flag. 0: read: source of last reset was not comparator0; write: comparator0 is not a reset source. 1: read: source of last reset was comparator0; write: comparator0 is a reset source (active-low). bit4: swrsf: software reset force and flag. 0: read: source of last reset was not a write to the swrsf bit; write: no effect. 1: read: source of last was a write to the swrsf bit; write: forces a system reset. bit3: wdtrsf: watchdog timer reset flag. 0: source of last reset was not a wdt timeout. 1: source of last reset was a wdt timeout. bit2: mcdrsf: missing clock detector flag. 0: read: source of last reset was not a missing clock detector timeout; write: missing clock detector disabled. 1: read: source of last reset was a missing clock detector timeout; write: missing clock detector enabled; triggers a reset if a missing clock condition is detected. bit1: porsf: power-on / vdd monitor reset flag. this bit is set anytime a power-on reset occu rs. writing this bit selects/deselects the vdd monitor as a reset source. note: writing ?1? to this bit before the vdd monitor is enabled and stabilized can cause a system reset. see register vdm0cn (figure 10.1). 0: read: last reset was not a power-on or vdd monitor reset; write: vdd monitor is not a reset source. 1: read: last reset was a power-on or vdd monitor reset; all other reset flags indetermi- nate; write: vdd monitor is a reset source. bit0: pinrsf: hw pin reset flag. 0: source of last re set was not /rst pin. 1: source of last reset was /rst pin. note: for bits that act as both reset source enables (on a write) and reset indicator flags (on a read), read-modify-write instruct ions read and modify the source enable only. this applies to bits: usbrsf, c0rsef, swrsf, mcdrsf, porsf. r/w r r/w r/w r r/w r/w r reset value usbrsf ferror c0rsef swrsf wdtrsf mcdrsf porsf pinrsf variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xef rstsrc: reset source
table 10.1. reset electrical characteristics -40c to +85c unless otherwise specified. rev. 1.4 105 c8051f320/1 parameter conditions min typ max units /rst output low voltage i ol = 8.5 ma, vdd = 2.7 v to 3.6 v 0.6 v /rst input high voltage 0.7 x vdd v /rst input low voltage 0.3 x vdd /rst input pull-up curr ent /rst = 0.0 v 25 40 a vdd por threshold (v rst ) 2.40 2.55 2.70 v missing clock detector timeout time from last system clock rising edge to reset initiation 100 220 500 s reset time delay delay between release of any reset source and code execution at location 0x0000 5.0 s minimum /rst low time to generate a system reset 15 s vdd monitor turn-on time 100 s vdd monitor supply current 20 50 a
c8051f320/1 106 rev. 1.4 11. flash memory on-chip, re-programmable flash memory is included fo r program code and non-volatile data storage. the flash memory can be programmed in-system, a single by te at a time, through the c2 interface or by soft - ware using the movx instruction. once cleared to logic 0, a f lash bit must be erased to set it back to logic 1. flash bytes would typically be erased (set to 0xff) before being reprogrammed. the write and erase operations are automatically timed by hardware for pr oper execution; data pollin g to determine the end of the write/erase operation is not required. code execut ion is stalled during a flash write/erase operation. refer to ta b l e 11.1 for complete flash memory electrical characteristics. 11.1. programming the flash memory the simplest means of programming the flash memory is through the c2 interface using programming tools provided by silicon labs or a third party vendor. this is the only means for programming a non-initial - ized device. for details on the c2 commands to program flash memory, see section ?21. c2 interface? on page 245 . to ensure the integrity of flash contents, it is strongly recommended that the on-chip vdd monitor be enabled in any system that includes code that writes and/or erases flash memory from soft - ware. 11.1.1. flash lock and key functions flash writes and erases by user so ftware are protected with a lock and key function. the flash lock and key register (flkey) must be writ ten with the correct key codes, in sequence, be fore flash operations may be performed. the key codes are: 0xa5, 0xf1. the timing does not matter, but the codes must be written in order. if the key codes are written out of or der, or the wrong codes are written, flash writes and erases will be disabled until the next system reset. flash writes and eras es will also be disabled if a flash write or erase is attempted before the key codes have been written properly. the flash lock resets after each write or erase; the key codes must be writte n again before a following flash operation can be per - formed. the flkey regist er is det ailed in figure 11.2 . 11.1.2. flash erase procedure the flash memory can be programmed by software using the movx write instru ction with the address and data byte to be programmed provided as normal ope rands. before writing to flash memory using movx, flash write operations must be enabled by: (1) writi ng the flash key codes in sequence to the flash lock register (flkey); and (2) setting the pswe program st ore write enable bit (psc tl.0) to logic 1 (this directs the movx writes to target flash memory). the pswe bit remains set until cleared by software. a write to flash memory can clear bits to logic 0 but cann ot set them; only an erase operation can set bits to logic 1 in flash. a byte location to be programmed must be erased before a new value is written. the flash memory is organized in 512-byte pages. the erase operation applies to an entire page (setting all bytes in the page to 0xff). to erase an en tire 512-byte page, perform the following steps: step 1. disable interrupts (recommended). s tep 2. write the first key code to flkey: 0xa5. step 3. write the second key code to flkey: 0xf1. step 4. set the psee bit (register psctl). step 5. set the pswe bit (register psctl). step 6. using the movx instruction, write a data byte to any location within the 512-byte page to be erased. step 7. clear the pswe bit (register psctl). step 8. clear the psee bit (register pscti).
rev. 1.4 107 c8051f320/1 11.1.3. flash write procedure flash bytes are programmed by software with the following sequence: step 1. disable interrupts (recommended). s t ep 2. erase the 512-byte flash page containing the target location, as described in section 11.1.2. step 3. write the first key code to flkey: 0xa5. step 4. write the second key code to flkey: 0xf1. step 5. set the pswe bit (register psctl). step 6. clear the psee bit (register psctl). step 7. using the movx instruction, write a single data byte to the desired location within the 512- byte sector. step 8. clear the pswe bit (register psctl). steps 3-8 must be repeated for each byte to be written. after flash writes are complete, pswe should be clea re d so that movx instructions do not target program memory. table 11.1. flash electrical characteristics *note: 512 bytes at location 0x3e00 to 0x3fff are reserved. 11.2. non-volatile data storage the flash memory can be used for non-volatile data storage as well as program code. this allows data such as calibration coefficients to be calculated and stored at run time. data is written using the movx write instruction and read using the movc instructi on. note: movx read instructions always target xram. parameter conditions min typ max units fla s h size c8051f320/1 16384* bytes endurance 20k 100k erase/write erase cycle time 25 mhz system clock 10 15 20 ms write cycle time 25 mhz system clock 40 55 70 s
c8051f320/1 108 rev. 1.4 11.3. security options the cip-51 provides security options to protect the flash memory from inadvertent modification by soft - ware as well as to prevent the viewing of proprietary program code and constants. the program store w r ite enable (bit pswe in register psctl) and the program store erase enable (bit psee in register psctl) bits protect the flash memory from accidental modification by software. pswe must be explicitly set to ?1? before software can modify the flash me mory; both pswe and psee must be set to ?1? before software can erase flash memory. additional security features prevent proprietary program code and data constants from being read or altered across the c2 interface. a security lock byte located at the last byte of flash user space offers protection of the flash program memory from access (reads, writes, or erases) by unpr otected code or the c2 interface. the flash security mechanism allows the user to lock n 512-byte flash pages, starting at page 0 (addresses 0x0000 to 0x01f f), w here n is the 1?s compliment number represented by the security lock byte. see example below. important notes about the flash security: 1. clearing any bit of the lock byte to ?0? w ill lock the flash page containing the lock byte (in addition to the selected pages). 2. locked pages cannot be read, written, or erased via the c2 interface. 3. locked pages cannot be read, written, or eras e d by user firmware executing from unlocked memory space. 4. user firmware executing in a locked page may re ad and write flash memory in any locked or unlocked page excluding the reserved area. 5. user firmware executing in a locked page ma y er ase f lash memory in any locked or unlocked page excluding the reserved area and the page containing the lock byte. 6. locked pages can only be unlocked through the c2 interface with a c2 device erase com - mand. 7. if a user firmware flash access attempt is deni e d (per restrictions #3, #4, and #5 above), a flash error system reset will be generated. access limit set according to the flash security lock byte c8051f320/1 0x0000 0x3dff lock byte reserved 0x3dfe 0x3e00 flash memory organized in 512-byte pages 0x3c00 unlocked flash pages locked when any other flash pages are locked figure 11.1. flash program me mory map and security byte security lock byte: 11111101b 1?s compliment: 00000010b flash pages locked: 2 addresses locked: 0x0000 to 0x03ff
rev. 1.4 109 c8051f320/1 the level of flash security depends on the flash ac cess method. the three flash access methods that can be restricted are reads, writes, an d erases from the c2 debug interface, user firmware executing on unlocked pages, and user firmware executing on locked pages. ta b l e 11.2 summarizes the flash security features of the 'f320/1 devices. table 11.2. flash security summary action c2 debug interface user firmware executing from: an unlocked page a locked page read, write or erase unlocked pages ( e xcept page with lock byte) permitted permitted permitted read, write or erase locked pages ( e xcept page with lock byte) not permitted fedr permitted read or write page containing lock byte ( i f no pages are locked) permitted permitted permitted read or write page containing lock byte (if an y p age is locked) not permitted fedr permitted read contents of lock byte ? (if no pages are locked) permitted permitted permitted read contents of lock byte ? (if any page is locked) not permitted fedr permitted erase page containing lock byte ( i f no pages are locked) permitted fedr fedr erase page containing lock byte - unlock all pages (if an y p age is locked) only c2de fedr fedr lock additional pages (cha ng e '1's to '0's in the lock byte) not permitted fedr fedr unlock individual pages ? (change '0's to '1's in the lock byte) not permitted fedr fedr read, write or erase reserved area not permitted fedr fedr ? c2de - c2 device erase (erases all flash pages including the page containing the lock byte) fedr - not permitted; causes flash error device res e t (ferror bit in rstsrc is '1' after reset) ? - all prohibited operations that are performed via the c2 in te rface are ignored (do not cause device reset). - locking any flash page also locks th e p age containing the lock byte. - once written to, the lock byte cannot be modifi e d except by performing a c2 device erase. - if user code writes to the lock byte, the lock do es not t ake effect until the next device reset.
c8051f320/1 110 rev. 1.4 11.4. flash write and erase guidelines any system which contains routines which write or er ase flash memory from software involves some risk that the write or erase ro utines will execute unin tentionally if the cpu is op erating outside its specified operating range of vdd, system clock frequency, or te mperature. this accidental execution of flash modi - fying code can result in alteration of flash memory conte nts causing a system failure that is only recover - able by re-flashing the code in the device. to help prevent the accidental modi fica tion of flash by firmware, the vdd monitor must be enabled and enabled as a reset source on c8051f32x devices for the flash to be successfully modified. if either the vdd monitor or the vdd monitor reset source is not enabled, a flash error device reset will be generated when the firmware attempts to modify the flash. the following guidelines are recomme nded f or any system that contains routines which write or erase flash from code. 11.4.1. vdd maintenance and the vdd monitor 1. if the system power supply is subject to volta ge or current "spikes," add sufficient transient protection devices to the power supply to ensure that the supply voltages listed in the absolute maximum ratings table are not exceeded. 2. make certain that the minimum vdd rise time sp ecifica tion of 1 ms is met. if the system cannot meet this rise time specification, then add an ex ternal vdd brownout circ uit to the /rst pin of the device that holds the device in reset until vdd reaches 2.7 v and re-asserts /rst if vdd drops below 2.7 v. 3. keep the on-chip vdd monitor enabled and en able the vdd monitor as a reset source as early in code as possible. this should be the fi rst set of instructions executed after the reset vector. for 'c'-based systems, this will involv e modifying the startup code added by the 'c' compiler. see your compiler documentation for more details. make certain that there are no delays in software between enabling the vdd monitor and enabling the vdd monitor as a reset source. code examples showing this can be found in an201, "writing to flash from firmware", available from the silicon laboratories web site. 4. as an added precaution, explicitly enable the vdd monitor and enable the vdd monitor as a r eset source inside the functions that write and erase flash memory. the vdd monitor enable instructions should be placed just after the in struction to set pswe to a '1', but before the flash write or erase operation instruction. 5. make certain that all writes to the rstsrc (r eset sour ces) register use direct assignment operators and explicitly do not use the bit- wise operators (such as and or or). for exam - ple, "rstsrc = 0x02" is correct, but "rstsrc |= 0x02" is incorrect. 6. make certain that all writes to the rstsrc regist e r explicitly set the porsf bit to a '1'. areas to check are initialization code which enables ot her reset sources, such as the missing clock detector or comparator, for example, and instru ctions which force a so ftware reset. a global search on "rstsrc" can quickly verify this.
rev. 1.4 111 c8051f320/1 11.4.2. 16.4.2 pswe maintenance 7. reduce the number of places in code where the pswe bit (b0 in psctl) is set to a '1'. there should be exactly one routine in code that sets pswe to a '1' to write flash bytes and one rou - tine in code that sets both pswe and psee both to a '1' to erase flash pages. 8. minimize the number of variable accesses while pswe is set to a '1'. handle pointer address updates and loop maintenance outside the "pswe = 1; ... pswe = 0;" area. code examples showing this can be found in an201, "writing to flash from firmware", available from the sili - con laboratories web site. 9. disable interrupts prior to setti ng pswe to a '1' and leave them disabled until after pswe has been reset to '0'. any interrup ts posted during the flash writ e or erase operation will be ser - viced in priority order after the flash operation has been completed and interrupts have been r e-enabled by software. 10. make certain that the flash write and erase pointer variables are not located in xram. see you r compiler documentation for instructions regard ing how to explicitly lo cate variables in dif - ferent memory areas. 11. add address bounds checking to the routines th at write or erase flash memory to ensure that a routine called with an illegal address does not re sult in modification of the flash. 11.4.3. system clock 12. if operating from an external crystal, be advised that crystal performance is susceptible to electrical interference and is sensitive to layout and to changes in temperature. if the system is operating in an electrically noi sy environment, use the internal oscillator or use an external cmos clock. 13. if operating from the ex ternal osc illator, switch to the internal oscillator during flash write or erase operations. the external oscillator can continue to run, and the cpu can switch back to the external oscillator after th e flash operation has completed.
c8051f320/1 112 rev. 1.4 sfr definition 11.1. bits7?3: unused: read = 00000b. write = don?t care. bit2: reserved. read = 0b. must write = 0b. bit1: psee: program store erase enable setting this bit (in combination with pswe) a llows an entire page of flash program memory to be erased. if this bit is logic 1 and flash writes are enabled (pswe is logic 1), a write to flash memory using the movx in struction will erase the entire page that contains the loca- tion addressed by the movx instruction. the va lue of the data byte written does not matter. 0: flash program memory erasure disabled. 1: flash program memory erasure enabled. bit0: pswe: program store write enable setting this bit allows writing a byte of data to the flash program memory using the movx write instruction. the flash location should be erased before writing data. 0: writes to flash program memory disabled. 1: writes to flash program memory enabled; the movx write instruction targets flash memory. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - reserved psee pswe 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8f psctl: program store r/w control sfr definition 11.2. bits7?0: flkey: flash lock and key register write: this register must be written to before flas h writes or erases can be performed. flash remains locked until this register is written to with the following key codes: 0xa5, 0xf1. the timing of the writes does not matter, as long as the codes are written in order. the key codes must be written for each flas h write or erase operation. flas h will be locked until the next system reset if the wrong codes are written or if a flash operation is attempted before the codes have been written correctly. read: when read, bits 1?0 indicate the current flash lock state. 00: flash is write/erase locked. 01: the first key code has been written (0xa5). 10: flash is unlocked (writes/erases allowed). 11: flash writes/erases disabled until the next reset. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb7 flkey: flash lock and key
rev. 1.4 113 c8051f320/1 sfr definition 11.3. bits7: fose: flash one-shot enable this bit enables the flash read one-shot. when the flash one-shot disabled, the flash sense amps are enabled for a full clock cycle during flash reads. at system clock frequen- cies below 10 mhz, disabling the flash one- shot will increase system power consumption. 0: flash one-shot disabled. 1: flash one-shot enabled. bits6?0: reserved. read = 000000b. must write 000000b. r/w r/w r/w r/w r/w r/w r/w r/w reset value fose reserved reserved reserved reserved reserved reserved reserved 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb6 flscl: flash scale
c8051f320/1 114 rev. 1.4 12. external ram the c8051f320/1 devices include 2048 bytes of on-chip xram. this xram space is split into user ram (add resses 0x0000 - 0x03ff) and usb0 fi fo space (addresses 0x0400 - 0x07ff). xram 1024 bytes 0x0000 0x03ff same 2048 bytes as from 0x0000 to 0x07ff, wrapped on 2 kb boundaries 0x0400 0xffff usb fifos 1024 bytes 0x07ff 0x0800 accessed through usb fifo registers accessed with the movx instruction figure 12.1. external ram memory map 12.1. accessing user xram xram can be accessed using the external move instruction (movx) and the data pointer (dptr), or using movx indirect addressing mode. if th e movx instruction is used with an 8-bit address operand (such as @r1), then the high byte of the 16-bit address is provided by the external memory interface control reg - ister (emi0cn as shown in figure 12.1 ). note: the movx instruction is also used for writes to the flash memory. see section ?11. flash memory? on page 106 for details. the movx in st ruction accesses xram b y default. for any of the addressing modes the upper 5 bits of the 16-bit external data memory address word are "don't cares". as a result, the 2048-byte ram is ma pped modulo style over the entire 64k external data memory address range. for example, the xram byte at address 0x0000 is al so at address 0x0800, 0x1000, 0x1800, 0x2000, etc. important note: the upper 1k of the 2k xram functions as usb fifo space. see section 12.2 for details on accessing this memory space. 12.2. accessing usb fifo space the upper 1k of xram func tions as usb fifo space. figure 12.2 shows an expanded view of the fifo space and user xram. fifo space is ac c e ssed via usb fifo registers; see section ?15.5. fifo manage - ment? on page 147 for more information on accessing these fifos. th e movx instru ction should not be used to load or modify usb data in the fifo space. unused areas of the fifo space may be used as gen er al pu rpose xram, accessible as described in sec - tion 12.1 . the fifo block operates on the usb clock domai n ; th us the usb clock must be active when accessing fifo space. note that the number of sysclk cycles required by the movx instruction is increased when accessing usb fifo space. important note: the usb clock must be ac tive when accessing fifo space.
endpoint0 (64 bytes) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff user xram (1024 bytes) 0x0000 0x03ff endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes) usb fifo space (usb clock domain) user xram space (system clock domain) sfr definition 12.1. bits7?3: unused: read = 00000b. write = don?t care. bits2?0: pgsel[2:0]: xram page select bits. the xram page select bits provide the high byte of the 16-bit external data memory address when using an 8-bit movx command, effectively selecting a 256-byte page of ram. the upper 5-bits are "don't cares", so th e 2k address blocks are repeated modulo over the entire 64k external data memory address space. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - pgsel2 pgsel1 pgsel0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xaa emi0cn: external memory interface control rev. 1.4 115 c8051f320/1 figure 12.2. xram memory map expanded view
c8051f320/1 116 rev. 1.4 13. oscillators c8051f320/1 devices include a programmable inte rnal oscillator, an external oscillator drive circuit, and a 4x clock multiplier. the internal o scillator can be enabled/di sabled and calibrated using the oscicn and oscicl registers, as shown in figure 13.1 . the system clock (sysclk) can be derived from the internal oscillator, external oscillator circui t, or the 4x clock multiplier divided by 2. the usb clock (usbclk) can be derived from the inte rnal oscillator, external oscillator, or 4x clock multiplier. oscillator electrical specifi - cations are given in ta b l e 13.3 on page 125 . clock multiplier osc exosc input circuit xtlvld xtal1 xtal2 option 2 vdd xtal2 option 1 10m ? option 3 xtal2 option 4 xtal2 oscxcn xtlvld xoscmd2 xoscmd1 xoscmd0 xfcn2 xfcn1 xfcn0 clkmul mulen mulinit mulrdy mulsel1 mulsel0 programmable internal clock generator en oscicl oscicn ioscen ifrdy suspend ifcn1 ifcn0 iosc n exosc / 2 x 2 x 2 exosc iosc sysclk exosc exosc / 2 exosc / 3 exosc / 4 iosc / 2 usbclk usbclk2-0 clksel usbclk2 usbclk1 usbclk0 clksl1 clksl0 figure 13.1. oscillator diagram 13.1. programmable internal oscillator all c8051f320/1 devices include a pr ogrammable internal oscillator that defaults as the system clock after a system reset. the in ternal oscillator period can be programmed via the oscicl register as defined by equation 13.1 , where f base is the frequency of the inter nal oscillator following a reset, ? t is the change in internal oscillator period, and ? oscicl is a c hange to the value held in register oscicl.
equation 13.1. typical change in inte rnal oscillator pe riod with oscicl ? t 0.0025 1 f base ------------ - ? oscicl ??? on c8051f320/1 devices, oscicl is factory calibrated to obtain a 12 mhz base frequency ( f base ). sec - tion 13.1.1 details oscillator programming fo r c8051f320/1 devices. electrical specifications for the preci - sion internal osc illator are given in table 13.3 on page 125 . note that the system clock may be derived from the programmed internal oscillator divided by 1, 2, 4, or 8, as defin ed by the ifcn bits in register oscicn. the divide value defaults to 8 following a reset. the oscicl reset value is factory calibrated to result in a 12 mhz internal os cillator with a 1.5% accu - racy; this frequency is suitable for u s e as the usb clock (see section 13.4 ). software may modify the fre - quency of the internal oscillator as described below . important note: onc e the internal o scillator frequency has been modified, the internal os cillator may not be used as the usb clock as described in section 13.4 . the internal oscillator frequency w ill reset to it s original factory-calibra ted frequency following any dev i ce reset, at which point th e oscillator is suitable for use as the usb clock. software should read and adjust the value of oscicl according to equation 13.1 to obtain the desired fre - quency. the example below shows how to obtain an 11.6 mhz internal oscillator frequency. f base is the internal osc illator reset frequency; t base is the reset oscillator period. f des is the desired internal oscillator frequency; t des is the desired oscillator period. the required change in period ( ? ) is the difference between the base period and the desired period. using equation 13.1 and th e above calculations, find ? : ? is rounded to the nearest integer (14) and added to the reset value of register oscicl. f base 12000000 hz = t base 1 12000000 ------------- ---------- - s = f des 11600000 hz = t des 1 11600000 ------------- ---------- - s = ? t des 1 11600000 --------------- -------- - 1 12000000 ------------- ---------- - ? 2.87 10 9? ? s == 2.87 10 9? ? 0.0025 1 f base ------------ - ? oscicl ?? = ? oscicl 13.79= rev. 1.4 117 c8051f320/1 13.1.1. programming the internal oscillator on c8051f320/1 devices
c8051f320/1 118 rev. 1.4 important note: if the sum of the reset value of oscicl and ? oscicl is greater than 31 or less than 0, then the device will not be capable of producing the desired frequency. 13.1.2. internal oscillator suspend mode the internal oscillato r may be placed in suspend mode by writing ?1? to the suspend bit in register oscicn. in suspend mode, the intern al oscillator is stopped until a non-idle usb event is detected ( sec - tion 15 ) or vbus matches the polarity selected by the vbpol bit in register reg0cn ( section 8.2 ). the transceiver is able to detect non-idle usb events even when it is placed in suspend mode. on a non-idle usb event, a resume interrupt is generated, on receipt of which the phyen bit should be set to '1' to re- enable the transceiver. sfr definition 13.1. oscicn: internal os cillator control sfr definition 13.2. oscicl: internal osci llat or calibration bit7: ioscen: internal oscillator enable bit. 0: internal oscillator disabled. 1: internal oscillator enabled. bit6: ifrdy: internal osc illator frequency ready flag. 0: internal oscillator is not running at prog rammed frequency. 1: internal oscillator is ru nning at programmed frequency. bit5: suspend: force suspend writing a ?1? to this bit will force the internal o scillator to be stopped. the oscillator will be re- started on the next non-idle usb event (i.e., resume signaling) or vbus interrupt event (see figure 8.1). bits4?2: unused. read = 000b, write = don't care. bits1?0: ifcn1?0: internal osc illator frequency control bits. 00: sysclk derived from internal oscillator divided by 8. 01: sysclk derived from internal oscillator divided by 4. 10: sysclk derived from internal oscillator divided by 2. 11: sysclk derived from intern al oscillator divided by 1. r/w r r/w r r/w r/w r/w r/w reset value ioscen ifrdy suspend - - - ifcn1 ifcn0 10000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb2 bits7?5: unused: read = varies. write = don?t care. bits4?0: osccal: oscillator calibration value these bits determine the internal o scillator period as pe r equation 13.1. note: the contents of this register are undefined when clock recovery is enabled. see section ?15.4. usb clock configuration? on page 146 for details on clock recovery. r/w r/w r/w r/w r/w r/w r/w r/w reset value --- osccal variable bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb3
rev. 1.4 119 c8051f320/1 13.2. external oscill ator drive circuit the external oscillator circuit may drive an external cr ystal, ceramic resona tor, capacitor, or rc network. a cmos clock may also provide a clock input. for a cr ystal or ceramic resonator configuration, the crys - tal/resonator must be wired across the xtal 1 and xtal2 pins as shown in option 1 of figure 13.1 . a 10 m ?? r esistor also must be wired across the xtal1 an d xtal2 pins for the crystal/resonator configura - tion. in rc, capacitor, or cmos cl o ck configuration, the clock source should be wired to the xtal2 pin as shown in option 2, 3, or 4 of figure 13.1 . the type of external oscillator must be selected in the oscxcn register, and the frequency control bits (xfcn) must be selected appropriately (see figure 13.3 ) important note on external oscillator usage: po rt pins must be configured when using the external oscillator circuit. when the external oscillator drive ci rcuit is enabled in crystal/resonator mode, port pins p0.2 and p0.3 are used as xtal1 and xtal2 respectively. when the ex ternal oscillator drive circuit is enabled in capacitor, rc, or cmos clock mode, port pin p0.3 is used as xtal2. the port i/o crossbar should be configured to skip the port pins used by the oscillator circuit; see section ?14.1. priority crossbar decoder? on page 128 for crossbar configuration. additionally , when using the ex ternal oscillator circuit in crystal/resonator, capacitor, or rc mode, the associated port pins should be configured as ana log inputs . in cmos clock mode, the associated pin should be configured as a digital input . see section ?14.2. port i/o initialization? on page 130 for details on port input mode s election. 13.2.1. clocking timers directly through the external oscillator the external oscillator source divided by eight is a clock option for the timers ( section ?19. timers? on page 209 ) and the programmable counter array (pca) ( section ?20. programmable counter array (pca0)? on page 227 ). when the external oscillator is used to clock these peripherals, but is not used as the system clock, the external o scillator frequency must be less than or equal to the system clock fre - quency. in this configuration, the clock supplied to the peripheral (exter nal oscillator / 8) is synchronized with the system clock; the jitter associated with this sy nchronization is limited to 0.5 system clock cycles. 13.2.2. external crystal example if a crystal or ceramic resonator is used as an external oscillator source for the mcu, the circuit should be configured as shown in figure 13.1 , option 1. the external oscillato r frequency contro l value (xfcn) should be chosen from the crystal column of the table in figure 13.3 (oscxcn register). for example, a 12 mhz crystal requires an xfcn setting of 111b. when the crystal oscillator is first e nabled, the oscillator amplitude detecti on circuit requires a settling time to achieve proper bias. introducing a delay of 1 ms between enabling the o scillator and c hecking the xtlvld bit will prevent a premature switch to the extern al oscillator as the system clock. switching to the external oscillator before the crysta l oscillator has stabilized can result in unpredictable behavior. the rec - ommended procedure is: step 1. enable the external oscillator. s tep 2. wait at least 1 ms. step 3. poll for xtlvld => ?1?. step 4. switch the system cl ock to the external oscillator. important note on external crystals: crystal oscillator circuits are qui te sensitive to pcb layout. the crystal should be placed as close as possible to the xtal pins on the device. the traces should be as short as possible and shielded with ground plane fr om any other traces which could introduce noise or interference.
c8051f320/1 120 rev. 1.4 13.2.3. external rc example if an rc network is used as an external oscillator so urce for the mcu, the circ uit should be configured as shown in figure 13.1 , option 2. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasitic capacitance in the pcb layout. to deter - mine the required external oscilla tor frequency control va lue (xfcn) in the oscxcn register, first select the rc network value to prod uce the desired frequency of oscilla tion. if the frequency desired is 100 khz, let r = 246 k? an d c = 50 pf: f = 1.23( 10 3 ) / rc = 1.23 ( 10 3 ) / [ 246 x 50 ] = 0.1 mhz = 100 khz referring to the table in figure 13.3 , the required xfcn setting is 010b. programming xfcn to a higher setting in rc mode will improve frequency acc uracy at an increased ex ternal oscillator supply current. 13.2.4. external capacitor example if a capacitor is used as an external oscillator for t he mcu, the circuit should be configured as shown in figure 13.1 , option 3. the capacitor should be no greater than 100 pf; however for very small capacitors, the total capacitance may be dominated by parasiti c ca pacitance in the pcb layout. to determine the required external oscillato r frequency control value (xfcn) in th e oscxcn register, select the capaci - tor to be used and find t he frequency of oscillation from the equations below. assume vdd = 3.0 v and c = 50 pf: f = kf / ( c x vdd ) = kf / ( 50 x 3 ) mhz f = kf / 150 mhz if a frequency of roughly 150 khz is desired, select the k factor from the table in figure 13.3 as kf = 22: f = 22 / 150 = 0.146 mhz, or 146 khz therefore, the xfcn value to use in this example is 011b.
rev. 1.4 121 c8051f320/1 sfr definition 13.3. oscxcn: external oscillator control bit7: xtlvld: crystal oscillator valid flag. (read only when xoscmd = 11x.) 0: crystal oscillator is un used or not yet stable. 1: crystal oscillator is running and stable. bits6?4: xoscmd2?0: extern al oscillator mode bits. 00x: external oscillator circuit off. 010: external cmos clock mode. 011: external cmos clock mode with divide by 2 stage. 100: rc oscillator mode. 101: capacitor oscillator mode. 110: crystal oscillator mode. 111: crystal oscillator mo de with divide by 2 stage. bit3: reserved. read = 0, write = don't care. bits2?0: xfcn2?0: external os cillator frequency control bits. 000?111: see table below: crystal mode (circuit from figure 13.1, option 1; xoscmd = 11x) choose xfcn value to match crystal or resonator frequency. rc mode (circuit from figure 13.1, option 2; xoscmd = 10x) choose xfcn value to match frequency range: f = 1.23(10 3 ) / (r * c) , where f = frequency of clock in mhz c = capacitor value in pf r = pull-up resistor value in k ? c mode (circuit from figure 13.1 , option 3; xoscmd = 10x) choose k factor (kf) for the oscillation frequency desired: f = kf / (c * vdd) , where f = frequency of clock in mhz c = capacitor value the xtal2 pin in pf vdd = power supply on mcu in volts r r/w r/w r/w r r/w r/w r/w reset value xtlvld xoscmd2 xoscmd1 xoscmd 0 - xfcn2 xfcn1 xfcn0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xb1 xfcn crystal (xoscmd = 11x) rc (xoscmd = 10x) c (xoscmd = 10x) 000 f ? 32 khz f ?? 25 khz k factor = 0.87 001 32 khz ?? f ?? 84 khz 25 khz ?? f ?? 50 khz k factor = 2.6 010 84 khz ? f ?? 225 khz 50 khz ?? f ?? 100 khz k factor = 7.7 011 225 khz ? f ?? 590 khz 100 khz ?? f ?? 200 khz k factor = 22 100 590 khz ? f ?? 1.5 mhz 200 khz ?? f ?? 400 khz k factor = 65 101 1.5 mhz ? f ?? 4 mhz 400 khz ?? f ?? 800 khz k factor = 180 110 4 mhz ? f ?? 10 mhz 800 khz ?? f ?? 1.6 mhz k factor = 664 111 10 mhz ? f ?? 30 mhz 1.6 mhz ?? f ?? 3.2 mhz k factor = 1590
c8051f320/1 122 rev. 1.4 13.3. 4x clock multiplier the 4x clock multiplier allows a 12 mhz oscillator to generate the 48 mhz clock required for full speed usb com munication (see section ?15.4. usb clock configuration? on page 146 ). a divided version of the multiplier output can also be us ed as the sy stem clock. see section 13.4 for details on system clock and usb clock source selection. the 4x clock multiplier is configured via the clkmul register. the procedure for configuring and enabling the 4x clock multiplie r is as follows: 1. reset the multiplier by writ in g 0x00 to register clkmul. 2. select the multiplier input source via the mulsel bits. 3. enable the multiplier with the mulen bit (clkmul | = 0x80). 4. delay for >5 s. 5. initialize the multip lier w ith the mulinit bit (clkmul | = 0xc0). 6. poll for mulrdy => ?1?. important note: when using an external oscillator as the input to the 4x clock multiplier, the exter - nal source must be enabled and stable be fo re the multiplier is initialized. see section 13.4 for details on selecting an external oscillator source. sfr definition 13.4. clkmul: clock multiplier control bit7: mulen: clock multiplier enable 0: clock multiplier disabled. 1: clock multiplier enabled. bit6: mulinit: clock multiplier initialize this bit should be a ?0? when the clock multip lier is enabled. once ena bled, writing a ?1? to this bit will initialize the clock mu ltiplier. the mulrdy bit reads ?1? when the clock multiplier is stabilized. bit5: mulrdy: clock multiplier ready this read-only bit indicates the status of the clock multiplier. 0: clock multiplier not ready. 1: clock multiplier ready (locked). bits4?2: unused. read = 000b; write = don?t care. bits1?0: mulsel: clock mu ltiplier input select these bits select the clock supplied to the clock multiplier. r/w r/w r r/w r/w r/w r/w r/w reset value mulen mulinit mulrdy - - - mulsel 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address 0xb9 mulsel selected clock 00 internal oscillator 01 external oscillator 10 external oscillator / 2 11 reserved
rev. 1.4 123 c8051f320/1 13.4. system and us b clock selection the internal oscillator requir es little start-up time and may be sele cted as the system or usb clock immedi - ately following the oscicn wr ite that enables the internal oscillator . external crystals and ceramic resona - tors typically require a start-up time before they are settled and ready for use. the crystal valid flag (xtl vld in register oscxcn) is set to ?1? by hardware when the external oscillator is settled. to avoid reading a false xtlvld, in crystal mode software should delay at least 1 ms between enabling the e xternal oscillator and checking xtlvld. rc and c modes typically require no startup time. 13.4.1. system clock selection the clksl[1:0] bits in register cl ksel select which osc illator source is used as the system clock. clksl[1:0] must be set to 01b for the system clock to run from th e external oscillator; however the exter - nal oscillator may still clock certain pe ripherals (timers, pca , usb) when the internal oscillator is selected as the system clock. the system clock may be switched on-the-fly between the inte rnal oscillator, external oscillator, and 4x clock multiplier so long as the selected oscillator is enabled and has settled. 13.4.2. usb clock selection the usbclk[2:0] bits in register clksel select which oscillator source is used as the usb clock. the usb clock may be derived from the 4x clock multiplier output, a divided version of the internal oscillator, or a divided version of the exte rnal oscillator. note that the usb clock must be 48 mhz when operating usb0 as a full speed function; the usb clock must be 6 mhz when operating usb0 as a low speed function. see figure 13.5 for usb clock selection options. some example usb clock configurations for full and low speed mode are given below: table 13.1. typical usb full sp eed clock settings internal oscillator clock signal input source selection register bit settings usb clock clock multiplier usbclk = 000b clock multiplier input internal oscillator* mulsel = 00b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings usb clock clock multiplier usbclk = 000b clock multiplier input external oscillator mulsel = 01b external oscillator crystal oscillator mode 12 mhz crystal xoscmd = 110b xfcn = 111b *note: clock recovery must be enabled for this configuration.
c8051f320/1 124 rev. 1.4 sfr definition 13.5. clksel: clock select table 13.2. typical usb low speed clock settings internal oscillator clock signal input source selection register bit settings usb clock internal oscillator/2 usbclk = 001b internal oscillator divide by 1 ifcn = 11b external oscillator clock signal input source selection register bit settings usb clock external oscillator/4 usbclk = 101b external oscillator crystal oscillator mode 24 mhz crystal xoscmd = 110b xfcn = 111b bit 7: unused. read = 0b; write = don?t care. bits6?4: usbclk2?0: usb clock select these bits select the clock supplied to usb0. when operating usb0 in full-speed mode, the selected clock should be 48 mhz. when operating usb0 in low-speed mode, the selected clock should be 6 mhz. bits3?2: unused. read = 00b; write = don?t care. bits1?0: clksl1?0: system clock select these bits select the system clock source. r/w r/w r/w r/w r/w r/w r/w r/w reset value - usbclk - - clksl 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address 0xa9 usbclk selected clock 000 4x clock multiplier 001 internal oscillator/2 010 external oscillator 011 external oscillator/2 100 external oscillator/3 101 external oscillator/4 110 reserved 111 reserved clksl selected clock 00 internal oscillator (as determined by the ifcn bits in register oscicn) 01 external oscillator 10 4x clock multiplier/2 11 reserved
rev. 1.4 125 c8051f320/1 table 13.3. internal oscillator el ectrical characteristics ?40 to +85 c unless otherwise specified. parameter conditions min typ max units internal oscillator frequency r eset frequency 11.82 12 12.18 mhz internal oscillator supply current (from vdd) oscicn.7 = 1 450 a usb clock frequency* full speed mode low speed mode 47.88 5.91 48 6 48.12 6.09 mhz *note: applies only to external oscillator sources.
c8051f320/1 126 rev. 1.4 14. port input/output digital and analog resources are available through 25 i/o pins (c8051f320) or 21 i/o pins (c8051f321). port pins are organized as shown in figure 14.1 . each of the port pins can be defined as general-purpose i/o (gpio) or analog input; port pi n s p0.0-p2.3 can be assigned to one of the internal digital resources as shown in figure 14.3 . the designer has complete control over which function s ar e assigned, limited only by the number of physical i/o pins. this resource ass i gnme nt flexibility is achiev ed through the use of a priority crossbar decoder. note that the state of a port i/o pin can always be read in the corresponding port latch, regardless of the crossbar settings. the crossbar assigns the selected internal digital resou r ces to the i/o pins based on the priority decoder ( figure 14.3 and figure 14.4 ). the registers xbr0 and xbr1, defined in figure 14.1 and figure 14.2 , are used to select internal digital functions. all port i/os are 5 v tolerant (refer to figure 14.2 for the port cell circuit). the port i/o cells are configured as either push-pull or open-drain in the port outp ut m ode registers (pnmdout, where n = 0,1,2,3). com - plete electrical spec ifications for por t i/o are given in ta b l e 14.1 on page 138 . xbr0, xbr1, pnskip registers digital crossbar priority decoder 2 p0 i/o cells p0.0 p0.7 8 pnmdout, pnmdin registers uart (internal digital signals) highest priority lowest priority sysclk 2 smbus t0, t1 2 6 pca cp1 outputs 2 4 spi cp0 outputs 2 p1 i/o cells p1.0 p1.7 8 p2 i/o cells p2.0 p2.7 8 p3 i/o cells p3.0 1 (port latches) p0 (p0.0-p0.7) (p1.0-p1.7) (p2.0-p2.7) (p3.0) 8 8 8 8 p1 p2 p3 note: p2.4-p2.7 only available on the c8051f320 figure 14.1. port i/o fun ctional block diagram
gnd /port-outenable port-output push-pull vdd vdd /weak-pullup (weak) port pad analog input analog select port-input rev. 1.4 127 c8051f320/1 figure 14.2. port i/o cell block diagram
c8051f320/1 128 rev. 1.4 14.1. priority crossbar decoder the priority cro ssbar decoder ( figure 14.3 ) assigns a priority to each i/o function , starting at the top with uart0. when a digital resource is selected, the leas t- significant unassigned port pin is assigned to that resource (excluding uart0, which is a lways at pins 4 and 5). if a port pin is assigned, the crossbar skips that pin when assigning the next se lected resource. additionally, the crossbar will skip port pins whose associated bits in the pnskip registers are set. the pn skip registers allow software to skip port pins that are to be used for analog input, dedicated functions, or gpio. important note on crossbar configuration: i f a port pin is claimed by a peripheral without use of the crossbar, its corresponding pnskip bit should be set. this applies to p0.7 if vref is used, p0.3 and/or p0.2 if the external oscillator circuit is enabled, p0.6 if the adc is config ured to use the external conversion start signal (cnvstr), and any selected adc or comparator inputs. the crossbar skips selected pins as if they were already assigned, and moves to the next unassigned pin. figure 14.3 shows the crossbar decoder priority with no port pins sk ipped (p 0skip, p1skip, p2skip = 0x00); figure 14.4 shows the crossbar decoder priority with the xtal1 (p0. 2 ) and xtal2 (p0.3) pins skipped (p0skip = 0x0c). figure 14.3. crossbar priority decoder with no pins skipped xtal1 xtal2 cnvstr vref 012345670123456701234567 sck miso mosi nss* *nss is only pinned out in 4-wire spi mode cp0 cp0a cp1 00000000000000000000 special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals eci t0 t1 p0skip[0:7] p2skip[0:3] signals unavailable sf signals pin i/o tx0 rx0 sda scl p0 p2 cex3 cex4 p1skip[0:7] p1 cp1a cex2 cex0 cex1 sysclk
rev. 1.4 129 c8051f320/1 figure 14.4. crossbar priority d ecoder with crystal pins skipped registers xbr0 and xbr1 are used to assign the digital i/o resources to the physical i/o port pins. note that when the smbus is selected, the crossbar assi gns both pins associated with the smbus (sda and scl); when the uart is selected, the crossbar assign s both pins associated with the uart (tx and rx). uart0 pin assignments are fixed for bootloading purp oses: uart tx0 is always assigned to p0.4; uart rx0 is always assigned to p0.5. standard port i/os appear contiguously after the prioritized functions have been assigned. important note: th e spi can be operated in either 3-wire or 4-wire modes, depending on the state of the nssmd1-nssmd0 bits in register spi 0cn. according to the spi mode, the nss signal may or may not be routed to a port pin. xtal1 xtal2 cnvstr vref 012345670123456701234567 sck miso mosi nss* *nss is only pinned out in 4-wire spi mode cp0 cp0a cp1 00110000000000000000 special function signals are not assigned by the crossbar. when these signals are enabled, the crossbar must be manually configured to skip their corresponding port pins. port pin potentially available to peripheral sf signals eci t0 t1 p0skip[0:7] p2skip[0:3] p1skip[0:7] sf signals pin i/o tx0 rx0 sda scl p0 p1 p2 cp1a cex3 cex4 signals unavailable cex2 cex0 cex1 sysclk
c8051f320/1 130 rev. 1.4 14.2. port i/o initialization port i/o initialization cons ists of the following steps: step 1. select the input mode (analog or digital) for all port pins, using the port input mode r egister (pnmdin). step 2. select the output mode (open-drain or push -pull) for all port pins, using the port output mode register (pnmdout). step 3. select any pins to be skipped by the i/o crossbar using the port skip registers (pnskip). step 4. assign port pins to desired peripherals (xbr0, xbr1). step 5. enable the cr ossbar (xbare = ?1?). all port pins must be configured as either analog or dig ital inputs. any pins to be used as comparator or adc inputs should be configured as an analog inputs. when a pin is configured as an analog input, its weak pull-up, digital driver, and digital receiver are disabled. this process saves power and reduces noise on the analog input. pins configured as digital inputs may still be used by analog peripherals; however this practice is not recommended. to configure a port pin fo r digital input, write ?0? to the corresponding bit in register pnmdout, and write ?1? to the corresponding port latch (register pn). additionally, all analog input pins should be configur ed to be skipped by the crossbar (accomplished by setting the associated bits in pnskip). port input mode is set in the pnmdin register, where a ?1? indicates a digital input, and a ?0? indicates an analog input. all pins default to digital inputs on reset. see figure 14.4 for the pnmdin register details. the output driver characteristics of the i/o pins ar e d efined using the port output mode registers (pnmd - out). each port output driver can be configured as either open drain or push- pull. this selection is required even for the digital resources selected in the xbrn registers, and is not automatic. the only exception to this is the smbus (sda, scl) pins, which are configured as open-drain regardless of the pnmdout settings. when the weakpud bi t in xbr1 is ?0?, a we ak pull-up is enabled for all port i/o con - figured as open-drain. weakpud does not affect the pu sh-pull port i/o. furthermo re, the weak pull-up is turned off on an output that is driving a ?0? to avoid unnecessary power dissipation. registers xbr0 and xbr1 must be loaded with the approp r iate values to select the digital i/o functions required by the design. setting the xbare bit in xbr1 to ?1? enables the cross bar. until the crossbar is enabled, the external pins remain as standard port i/o (in input mode), regardless of the xbrn register settings. for given xbrn register settings, one can de termine the i/o pin-out us ing the priority decode table; as an alternative, the confi guration wizard utility of the silicon labs ide software will determine the port i/o pin-assignments based on the xbrn register settings. important note: t he crossbar must be enabled to use ports p0, p1, and p2.0-p2.3 as standard port i/o in output mode. these port output drivers are disabled while the crossbar is disabled. p2.4-p2.7 and p3.0 always function as standard gpio.
rev. 1.4 131 c8051f320/1 sfr definition 14.1. xbr0: port i/o cro ssb ar register 0 bit7: cp1ae: comparator1 asynchronous output enable 0: asynchronous cp1 unavailable at port pin. 1: asynchronous cp1 routed to port pin. bit6: cp1e: comparator1 output enable 0: cp1 unavailable at port pin. 1: cp1 routed to port pin. bit5: cp0ae: comparator0 asynchronous output enable 0: asynchronous cp0 unavailable at port pin. 1: asynchronous cp0 routed to port pin. bit4: cp0e: comparator0 output enable 0: cp0 unavailable at port pin. 1: cp0 routed to port pin. bit3: syscke: /sysclk output enable 0: /sysclk unavailable at port pin. 1: /sysclk output routed to port pin. bit2: smb0e: smbus i/o enable 0: smbus i/o unavailable at port pins. 1: smbus i/o routed to port pins. bit1: spi0e: spi i/o enable 0: spi i/o unavailable at port pins. 1: spi i/o routed to port pins. bit0: urt0e: uart i/o output enable 0: uart i/o unavailable at port pin. 1: uart tx0, rx0 routed to port pins p0.4 and p0.5. r/w r/w r/w r/w r/w r/w r/w r/w reset value cp1ae cp1e cp0ae cp0e syscke smb0e spi0e urt0e 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe1
c8051f320/1 132 rev. 1.4 sfr definition 14.2. xbr1: port i/o cro ssb ar register 1 14.3. general purpose port i/o port pins that remain unassigned by the crossbar and are not used by analog peripherals can be used for general purpose i/o. ports3-0 are accessed through co rresponding special function registers (sfrs) that are both byte addressable and bit addressable. when writing to a port, the valu e written to the sfr is latched to maintain the output data value at each pin. when reading, the logic levels of the port's input pins are returned regardless of the xbrn settings (i.e., even when the pin is assigned to another signal by the crossbar, the port register can always read its corres ponding port i/o pin). the exception to this is the execution of the read-modify-write instructions. the read-modify-write instructions when operating on a port sfr are the following: anl, or l, xrl, jbc, cpl, inc, dec, dj nz and mov, clr or setb, when the destination is an individual bit in a port sfr. fo r these instructions, the value of the register (not the pin) is read, modified, and written back to the sfr. bit7: weakpud: port i/o weak pull-up disable. 0: weak pull-ups enabled (except for ports whose i/o are configured as analog input or push-pull output). 1: weak pull-ups disabled. bit6: xbare: crossbar enable. 0: crossbar disabled; all port drivers disabled. 1: crossbar enabled. bit5: t1e: t1 enable 0: t1 unavailable at port pin. 1: t1 routed to port pin. bit4: t0e: t0 enable 0: t0 unavailable at port pin. 1: t0 routed to port pin. bit3: ecie: pca0 external counter input enable 0: eci unavailable at port pin. 1: eci routed to port pin. bits2?0: pca0me: pca modu le i/o enable bits. 000: all pca i/o unavailable at port pins. 001: cex0 routed to port pin. 010: cex0, cex1 routed to port pins. 011: cex0, cex1, cex2 routed to port pins. 100: cex0, cex1, cex2, cex3 routed to port pins. 101: cex0, cex1, cex2, cex3, cex4 routed to port pins. 110: reserved. 111: reserved. r/w r/w r/w r/w r/w r/w r/w r/w reset value weakpud xbare t1e t0e ecie pca0me 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xe2
rev. 1.4 133 c8051f320/1 sfr definition 14.3. p0: port0 register sfr definition 14.4. p0mdin: port0 input mode register sfr definition 14.5. p0mdout: port0 output mode register bits7?0: p0.[7:0] write - output appears on i/o pins per crossbar registers (when xbare = ?1?). 0: logic low output. 1: logic high output (high impedance if corresponding p0mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p0mdin. directly reads port pin when configured as digital input. 0: p0.n pin is logic low. 1: p0.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x80 bits7?0: analog input configuration bits for p0.7-p0.0 (respectively). port pins configured as analog inputs have th eir weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p0.n pin is configured as an analog input. 1: corresponding p0.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf1 bits7?0: output configuration bits for p0.7?p0.0 (respectively): ignored if corresponding bit in regis- ter p0mdin is logic 0. 0: corresponding p0.n output is open-drain. 1: corresponding p0.n output is push-pull. ( note : when sda and scl appear on any of the port i/o, each are open-drain regardless of the value of p0mdout). r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa4
c8051f320/1 134 rev. 1.4 sfr definition 14.6. p0skip: port0 skip register sfr definition 14.7. p1: port1 register sfr definition 14.8. p1mdin: port1 input mode register bits7?0: p0skip[7:0]: port0 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p0.n pin is not skipped by the crossbar. 1: corresponding p0.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd4 bits7?0: p1.[7:0] write - output appears on i/o pins per crossbar re gisters (when xbare = ?1?). 0: logic low output. 1: logic high output (high impedance if corresponding p1mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p1md in. directly reads port pin when configured as digital input. 0: p1.n pin is logic low. 1: p1.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x90 bits7?0: analog input configuration bi ts for p1.7-p1.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p1.n pin is configured as an analog input. 1: corresponding p1.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf2
rev. 1.4 135 c8051f320/1 sfr definition 14.9. p1mdout: port1 output mode register sfr definition 14.10. p1skip: port1 skip register sfr definition 14.11. p2: port2 register bits7?0: output configuration bits for p1.7-p1.0 (res pectively): ignored if corresponding bit in regis- ter p1mdin is logic 0. 0: corresponding p1.n output is open-drain. 1: corresponding p1.n output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa5 bits7?0: p1skip[7:0]: port1 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p1.n pin is not skipped by the crossbar. 1: corresponding p1.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd5 bits7?0: p2.[7:0] write - output appears on i/o pins per crossbar registers (when xbare = ?1?). 0: logic low output. 1: logic high output (high impedance if corresponding p2mdout.n bit = 0). read - always reads ?0? if selected as analog input in register p2mdin. directly reads port pin when configured as digital input. 0: p2.n pin is logic low. 1: p2.n pin is logic high. note: p2.7?p2.4 only available on c8051f320 de vices. writes to these ports do not require xbare = ?1?. r/w r/w r/w r/w r/w r/w r/w r/w reset value p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xa0
c8051f320/1 136 rev. 1.4 sfr definition 14.12. p2mdin: port2 input mode register sfr definition 14.13. p2mdout: port2 out put mode register sfr definition 14.14. p2skip: port2 skip register bits7?0: analog input configuration bits for p2.7?p2.0 (respectively). port pins configured as analog inputs have their weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p2.n pin is co nfigured as an analog input. 1: corresponding p2.n pin is not configured as an analog input. note: p2.7?p2.4 only available on c8051f320 devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf3 bits7?0: output configuration bits for p2.7?p2.0 (respectively): ignored if corresponding bit in regis- ter p2mdin is logic 0. 0: corresponding p2.n output is open-drain. 1: corresponding p2.n output is push-pull. note: p2.7?p2.4 only available on c8051f320 devices. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa6 bits7?4: unused. read = 0000b. write = don?t care. bits3?0: p2skip[3:0]: port2 crossbar skip enable bits. these bits select port pins to be skipped by the crossbar decoder. port pins used as ana- log inputs (for adc or comparator) or used as special functions (vref input, external oscil- lator circuit, cnvstr input) should be skipped by the crossbar. 0: corresponding p2.n pin is not skipped by the crossbar. 1: corresponding p2.n pin is skipped by the crossbar. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd6
rev. 1.4 137 c8051f320/1 sfr definition 14.15. p3: port3 register sfr definition 14.16. p3mdin: port3 input mode register sfr definition 14.17. p3mdout: port3 out put mode register bits7?0: p3.[7:0] write - output appears on i/o pins. 0: logic low output. 1: logic high output (high impedance if corresponding p3mdout.n bit = 0). read - always reads ?0? if select ed as analog input in register p3mdin. directly reads port pin when configured as digital input. 0: p3.n pin is logic low. 1: p3.n pin is logic high. r/w r/w r/w r/w r/w r/w r/w r/w reset value p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 11111111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xb0 bits7?1: unused. read = 0000000b; write = don?t care. bit0: analog input configuration bit for p3.0. port pins configured as analog inputs have th eir weak pull-up, digital driver, and digital receiver disabled. 0: corresponding p3.n pin is configured as an analog input. 1: corresponding p3.n pin is not configured as an analog input. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - - - - 00000001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf4 bits7?1: unused. read = 0000000b; write = don?t care. bit0: output configuration bit for p3.0; ignored if corresponding bit in register p3mdin is logic 0. 0: corresponding p3.n output is open-drain. 1: corresponding p3.n output is push-pull. r/w r/w r/w r/w r/w r/w r/w r/w reset value ------- 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa7
c8051f320/1 138 rev. 1.4 table 14.1. port i/o dc electri cal characteristics v dd = 2.7 to 3.6v, ?40 to +85 c unless otherwise specified. parameters conditions min typ max units output high voltage i oh = ?3 ma, port i/o push-pull i oh = ?10 a, port i/o push-pull i oh = ?10 ma, port i/o push-pull vdd ? 0.7 vdd ? 0.1 ? ? ? vdd ? 0.8 ? ? ? v output low voltage i ol = 8.5 ma i ol = 10 a i ol = 25 ma ? ? ? ? ? 1.0 0.6 0.1 ? v input high voltage 2.0 ? ? v input low voltage ??0.8v input leakage current weak pull-up off w eak pull-up on, v in = 0 v ? ? ? 25 1 50 a
note: this document assumes a comprehensive understanding of the usb protocol. terms and abbreviations used in this document are defined in the u sb specification. we encourage you to review the latest version of the usb specification before proceeding. *note: t he c8051f320/1 cannot be used as a usb host device. rev. 1.4 139 c8051f320/1 15. universal serial bus controller (usb) c8051f320/1 devices include a complete full/low sp eed usb function for usb peripheral implementa - tions*. the usb function controller (usb0) consists of a ser i al interface engine (sie), usb transceiver (including matching resistors and conf igurable pull-up resistors), 1k fifo block, and clock recovery mech - anism for crystal-less operation. no external com pon en ts are required. the usb function controller and transceiver is universal serial bus specification 2.0 compliant. transceiver serial interface engine (sie) usb fifos (1k ram) d+ d- vdd endpoint0 in/out endpoint1 in out endpoint2 in out endpoint3 in out data transfer control cip-51 core usb control, status, and interrupt registers figure 15.1. usb0 block diagram
c8051f320/1 140 rev. 1.4 15.1. endpoint addressing a total of eight endpoint pipes are available. the control endpoint (endpoint0) always functions as a bi-directional in/out endpoint. the other endpoints are implemented as three pairs of in/out endpoint pipes: 15.2. usb transceiver the usb transceiver is configured via the usb0xcn register shown in figure 15.1 . this configuration includes transceiver enable/disable, p ull-up resistor enab le/disable, and device speed selection (full or low speed). when bit speed = ?1?, usb0 operates as a full speed usb function, and the on-chip pull-up resistor (if enabled) appears on th e d+ pin. when bit speed = ?0?, u sb0 operates as a low speed usb function, and the on-chip pull-up resistor (if enabled) appears on the d- pin. bits4-0 of register usb0xcn can be used for transceiver testing as described in figure 15.1 . the pull-up resistor is enabled only when vbus is present (see section ?8.2. vbus detection? on page 67 for details on vbus detection). note: the usb clock should be active before the transceiver is enabled. table 15.1. endpoint addressing scheme endpoint associated pipes usb protocol address endpoint0 endpoint0 in 0x00 endpoint0 out 0x00 endpoint1 endpoint1 in 0x81 endpoint1 out 0x01 endpoint2 endpoint2 in 0x82 endpoint2 out 0x02 endpoint3 endpoint3 in 0x83 endpoint3 out 0x03
rev. 1.4 141 c8051f320/1 sfr definition 15.1. usb0xcn: usb0 transceiver control bit7: pren: internal pull-up resistor enable the location of the pull-up resistor (d+ or d?) is de termined by the speed bit. 0: internal pull-up resistor disabled (devic e effectively detached from the usb network). 1: internal pull-up resistor enabled when vbu s is present (device attached to the usb net- work). bit6: phyen: physical layer enable this bit enables/disables the usb0 physical layer transceiver. 0: transceiver disabled (suspend). 1: transceiver enabled (normal). bit5: speed: usb0 speed select this bit selects the usb0 speed. 0: usb0 operates as a low speed device. if ena bled, the internal pull-up resistor appears on the d? line. 1: usb0 operates as a full speed device. if enab led, the internal pull-up resistor appears on the d+ line. bits4?3: phytst1?0: physical layer test these bits can be used to test the usb0 transceiver. bit2: dfrec: differential receiver the state of this bit indicates the current differential value present on the d+ and d? lines when phyen = ?1?. 0: differential ?0? signaling on the bus. 1: differential ?1? signaling on the bus. bit1: dp: d+ signal status this bit indicates the current logic level of the d+ pin. 0: d+ signal currently at logic 0. 1: d+ signal currently at logic 1. bit0: dn: d- signal status this bit indicates the current logic level of the d? pin. 0: d? signal currently at logic 0. 1: d? signal currently at logic 1. r/w r/w r/w r/w r/w r r r reset value pren phyen speed phytst1 phytst0 dfrec dp dn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd7 phytst[1:0] mode d+ d? 00b mode 0: normal (non-test mode) x x 01b mode 1: differe ntial ?1? forced 1 0 10b mode 2: differe ntial ?0? forced 0 1 11b mode 3: single-ended ?0? forced 0 0
c8051f320/1 142 rev. 1.4 15.3. usb register access the usb0 controller registers listed in ta b l e 15.2 are accessed through two sfrs: usb0 address (usb0adr) and usb0 dat a (usb0dat). the usb0adr register se lects which usb register is targeted by reads/writes of the usb0dat register. see figure 15.2 . endpoint control/status registers ar e accessed by fir st writing the usb re gister index with the target end - point number. once the target endpoint number is writ te n to the index register, the control/status registers associated with the target endpoint may be a ccessed. see the ?indexed registers? section of ta b l e 15.2 for a list of endpoint control/status registers. note: the usb clock must be acti ve when accessing usb registers. figure 15.2. usb0 re gister access scheme usb controller fifo access index register endpoint0 control/ status registers endpoint1 control/ status registers endpoint2 control/ status registers endpoint3 control/ status registers common registers interrupt registers 8051 sfrs usb0adr usb0dat
rev. 1.4 143 c8051f320/1 sfr definition 15.2. usb0adr: usb0 indirect address bits7: busy: usb0 register read busy flag this bit is used during indirect usb0 register a ccesses. software should wr ite ?1? to this bit to initiate a read of the usb0 register target ed by the usbaddr bits (usb0adr.[5-0]). the target address and busy bit may be written in the same write to usb0adr. after busy is set to ?1?, hardware will clear busy when the targeted register da ta is ready in the usb0dat register. software should check busy for ?0? be fore writing to usb0dat. write: 0: no effect. 1: a usb0 indirect register re ad is initiated at the address specified by the usbaddr bits. read: 0: usb0dat register data is valid. 1: usb0 is busy accessing an indirect register; usb0dat register data is invalid. bit6: autord: usb0 register auto-read flag this bit is used for block fifo reads. 0: busy must be written manually for each usb0 indirect register read. 1: the next indirect register read will automatically be initiated when software reads usb0dat (usbaddr bits will not be changed). bits5?0: usbaddr: usb0 indi rect register address these bits hold a 6-bit address used to indirect ly access the usb0 core registers. table 15.2 lists the usb0 core registers and their indire ct addresses. reads and writes to usb0dat will target the register indi cated by the usbaddr bits. r/w r/w r/w r/w r/w r/w r/w r/w reset value busy autord usbaddr 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x96
c8051f320/1 144 rev. 1.4 sfr definition 15.3. usb0dat: usb0 data table 15.2. usb0 controller registers usb register name usb register address description page number interrupt registers in1int 0x02 endpoint0 and endpoints1-3 in interrupt flags 153 out1int 0x04 endpoints1-3 out interrupt flags 154 cmint 0x06 common usb interrupt flags 155 in1ie 0x07 endpoint0 and endpoints1-3 in interrupt enables 156 out1ie 0x09 endpoints1-3 out interrupt enables 156 cmie 0x0b common usb interrupt enables 157 common registers faddr 0x00 function address 149 power 0x01 power management 151 framel 0x0c frame number low byte 152 frameh 0x0d frame number high byte 152 index 0x0e endpoint index selection 145 clkrec 0x0f clock recovery control 146 fifon 0x20-0x23 endpoints0-3 fifos 148 this sfr is used to indirectly read and write usb0 registers. write procedure: 1. poll for busy (u sb0adr.7) => ?0?. 2. load the target usb0 re gister address into the usbad dr bits in register usb0adr. 3. write data to usb0dat. 4. repeat (step 2 may be skipped when writing to the same usb0 register). read procedure: 1. poll for busy (u sb0adr.7) => ?0?. 2. load the target usb0 re gister address into the usbad dr bits in register usb0adr. 3. write ?1? to the busy bit in register usb0adr (steps 2 and 3 can be performed in the same write). 4. poll for busy (u sb0adr.7) => ?0?. 5. read data from usb0dat. 6. repeat from step 2 (step 2 may be skipped wh en reading the same usb0 register; step 3 may be skipped when the autord bit (usb0adr.6) is logic 1). r/w r/w r/w r/w r/w r/w r/w r/w reset value usb0dat 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x97
rev. 1.4 145 c8051f320/1 usb register definition 15.4. index: usb0 endpoint index indexed registers e0csr 0x11 endpoint0 control / status 160 eincsrl endpoint in control / status low byte 163 eincsrh 0x12 endpoint in control / status high byte 164 eoutcsrl 0x14 endpoint out control / status low byte 166 eoutcsrh 0x15 endpoint out control / status high byte 167 e0cnt 0x16 number of received byte s in endpoint0 fifo 161 eoutcntl endpoint out packet count low byte 167 eoutcnth 0x17 endpoint out packet count high byte 167 table 15.2. usb0 controll er registers (continued) usb register name usb register address description page number bits7?4: unused. read = 0000b; write = don?t care. bits3?0: epsel: endpoint select these bits select which endpoint is targeted when indexed usb0 re gisters are accessed. r r r r r/w r/w r/w r/w reset value - - - - epsel 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x0e index target endpoint 0x0 0 0x1 1 0x2 2 0x3 3 0x4?0xf reserved
c8051f320/1 146 rev. 1.4 15.4. usb clock configuration usb0 is capable of communication as a full or low speed usb function. communication speed is selected via the speed bit in sfr usb0xcn. when operati ng as a low speed func tion, the usb0 clock must be 6 mhz. when operating as a full speed fu nction, the usb0 clock must be 48 mhz. clock options a re described in section ?13. oscillators? on page 116 . the usb0 clock is selected via sfr clksel (see figure 13.5 on page 124 ). clock recovery circuitry uses the inco ming usb data stream to adjust the internal oscillato r; this allows the internal oscillator (and 4x clock multiplier) to meet the requirements for usb clock tolerance. clock recovery should be used in the following configurations: when operating usb0 as a low speed function with clock recovery, software must write ?1? to the crlow bit to enable low speed clock recovery. clock recovery is typically no t necessary in low speed mode. single step mode can be used to help the clock reco ve ry circuitry to lock when high noise levels are pres - ent on the usb network. this mode is not requir e d (or recommended) in typical usb environments. usb register definition 15.5. clkrec: clock recovery control communication speed usb clock 4x clock multiplier input full speed 4x clock multiplier internal oscillator low speed interna l oscillator/2 n/a bit7: cre: clock recovery enable. this bit enables/disables the usb clock reco very feature. 0: clock recovery disabled. 1: clock recovery enabled. bit6: crssen: clock recovery single step. this bit forces the oscillator calibration into ?single-step? mode during clock recovery. 0: normal calibration mode. 1: single step mode. bit5: crlow: low speed clock recovery mode. this bit must be set to ?1? if clock recovery is used when operating as a low speed usb device. 0: full speed mode. 1: low speed mode. bits4?0: reserved. read = variable. must write = 1001b. r/w r/w r/w r/w r/w r/w r/w r/w reset value cre crssen crlow res erved 00001001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x0f
rev. 1.4 147 c8051f320/1 15.5. fifo management 1024 bytes of on-chip xram are used as fifo sp ace for usb0. this fifo space is split between endpoints0-3 as shown in figure 15.3 . fifo space allocated for endpoints1-3 is configurable as in, out, or both (split mode: half in, half out). figure 15.3. usb fifo allocation 15.5.1. fifo split mode the fifo space for endpoints1-3 can be split such that the upper half of the fifo space is used by the in endpoint, and the lower half is used by the out endpoint . for example: if the end point3 fifo is configured for split mode, the upper 256 bytes (0x0540 to 0x063f) are used by endpoint3 in and the lower 256 bytes (0x0440 to 0x053f) are used by endpoint3 out. if an endpoint fifo is not configured for split mode , that endpoint in/out pair?s fifos are combined to form a single in or out fifo. in this case only one direction of the endpoint in/out pair may be used at a time. the endpoint direction (in/out) is determined by the dirsel bit in the corresponding endpoint?s eincsrh register (see figure 15.20 ). endpoint0 (64 bytes) configurable as in, out, or both (split mode) free (64 bytes) 0x0400 0x043f 0x0440 0x063f 0x0640 0x073f 0x0740 0x07bf 0x07c0 0x07ff user xram (1024 bytes) 0x0000 0x03ff usb clock domain system clock domain endpoint1 (128 bytes) endpoint2 (256 bytes) endpoint3 (512 bytes)
c8051f320/1 148 rev. 1.4 15.5.2. fifo double buffering fifo slots for endpoints1-3 can be configured for double-buffered mode. in this mode, the maximum packet size is halved and the fifo may contain tw o packets at a time. this mode is available for endpoints1-3. when an endpoint is configured for split mode, double buffering may be enabled for the in endpoint and/or the out endpoint. when split mode is not enabled, double-buffering may be enabled for the entire endpoint fifo. see ta b l e 15.3 for a list of maximum packet sizes for each fifo configuration. 15.5.1. fifo access each endpoint fifo is accessed through a correspond ing fifon register. a read of an endpoint fifon register unloads one byte from the fifo; a write of an endpoi nt fifon register loads one byte into the end - point fifo. when an endpoint fifo is configured for s plit mode, a read of the endpoint fifon register unloads one byte from the out endpoint fifo; a write of the endpoint fifon register loads one byte into the in endpoint fifo. usb register definition 15.6. fifon: usb0 endpoint fifo access table 15.3. fifo configurations endpoint number split mode enabled? maximum in packet size (double buffer disabled/enabled) maximum out packet size (double buffer disabled/enabled) 0n/a 64 1 n 128/64 y 64/32 64/32 2 n 256/128 y128/64 128/64 3 n 512/256 y 256/128 256/128 usb addresses 0x20?0x23 provide access to the 4 pairs of endpoint fifos: writing to the fifo address loads data into the in fifo for the corresponding endpoint. reading from the fifo address unloads data from the out fifo for the corresponding endpoint. r/w r/w r/w r/w r/w r/w r/w r/w reset value fifodata 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x20 - 0x23 in/out endpoint fifo usb address 0 0x20 1 0x21 2 0x22 3 0x23
rev. 1.4 149 c8051f320/1 15.6. function addressing the faddr register holds the current usb0 function address. software should write the host-assigned 7-bit function address to the faddr register when received as part of a set_address command. a new address written to faddr will not take effect (usb0 will not respond to the new ad dress) until the end of the current transfer (typic ally following the status phase of the set_address command transfer). the update bit (faddr.7) is set to ?1? by hardware when software writes a new address to the faddr regis - ter. hardware clears the update bit when the new address takes effect as described above. usb register definition 15.7. faddr: usb0 function address 15.7. function configur ation and control the usb register power ( figure 15.8 ) is used to configure and control usb0 at the device level (enable/ disable, reset/suspend/resume handling, etc.). usb reset: the u sbrst bit (power.3) is set to ?1? by ha rdware when reset signaling is detected on the bus. upon this dete ction, the following occur: 1. the usb0 address is reset (faddr = 0x00). 2. endpoint fifos are flushed. 3. control/status registers are reset to 0x 00 (e0csr, eincsrl, eincsrh, eoutcsrl, eoutcsrh). 4. usb register index is reset to 0x00. 5. all usb interrupts (excluding the suspend interrupt) are enabled and their corresponding flags clea red. 6. a usb reset interrupt is generated if enabled. writing a ?1? to the usbrst bit will generate an asynchronous u sb0 reset. all u sb registers are reset to their default values following this asynchronous reset. suspend mode: with sus pend detection enabled (susen = ?1?), usb0 will enter suspend mode when suspend signaling is detect ed on the bus. an interrupt will be gene rated if enabled (s usinte = ?1?). the suspend interrupt service routine (isr) should perfor m application-specific conf iguration tasks such as bit7: update: function address update set to ?1? when software writes the faddr regist er. usb0 clears this bit to ?0? when the new address takes effect. 0: the last address written to faddr is in effect. 1: the last address written to faddr is not yet in effect. bits6?0: function address holds the 7-bit function address for usb0. this address should be written by software when the set_address standard device request is received on en dpoint0. the new address takes effect when the de vice request completes. r r/w r/w r/w r/w r/w r/w r/w reset value update function address 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x00
c8051f320/1 150 rev. 1.4 disabling appropriate peripherals and/or configuring clock sources for low power modes. see section ?13. oscillators? on page 116 for more details on internal oscillato r configuration, in cluding the suspend mode feature of the internal oscillator . usb0 exits suspend mode when any of the following occur: (1) resume signaling is detected or gener - ated, (2) reset signaling is detected, or (3) a device or usb r eset occurs. if suspended, the internal oscil - lator will exit suspend mode upon any of the above listed events. resume signaling: usb0 w ill exit suspend mode if resume signaling is detected on the bus. a resume interrupt will be generated upon detection if enabled (resinte = ?1?). software may force a remote wakeup by writing ?1? to the resume bit (power.2). when forcing a remote wakeup, software should write resume = ?0? to en d resume signaling 10-15 ms after the remote wakeup is initiated (resume = ?1?). iso update: when sof tware writes ?1? to the isoup bit (power.7), th e iso update function is enabled. with iso update enabled, new packe ts written to an iso in endpoint will not be transmitted until a new start-of-frame (sof) is re ceived. if the iso in endpoint receives an in token before a sof, usb0 will transmit a zero-length packet. when isoup = ?1?, iso update is enabled for all iso endpoints. usb enable: usb0 is disabled following a power-on-reset (por). usb0 is enabled by clearing the usbinh bit (power.4). once written to ?0?, the usbinh can only be set to ?1? by one of the following: (1) a power-on-reset (por), or (2) an asynchronous usb0 reset generated by writing ?1? to the usbrst bit (power.3). software should perform all usb0 configu ration before enabling usb0. the configuration sequence should be performed as follows: step 1. select and enable the usb clock source. s tep 2. reset usb0 by writing usbrst= ?1?. step 3. configure and enable the usb transceiver. step 4. perform any usb0 function configuration (interrupts, suspend detect). step 5. enable usb0 by writing usbinh = ?0?.
rev. 1.4 151 c8051f320/1 usb register definition 15.8. power: usb0 power bit7: isoud: iso update this bit affects all in isochronous endpoints. 0: when software writes inprdy = ?1?, usb0 will send the packet when the next in token is received. 1: when software writes inprdy = ?1?, u sb0 will wait for a sof to ken before sending the packet. if an in token is received before a sof token, usb0 will send a zero-length data packet. bits6?5: unused. read = 00b. write = don?t care. bit4: usbinh: usb0 inhibit this bit is set to ?1? followin g a power-on reset (por) or an asynchronous usb0 reset (see bit3: reset). software should cl ear this bit after all usb0 an d transceiver initialization is complete. software cannot set this bit to ?1?. 0: usb0 enabled. 1: usb0 inhibited. all usb traffic is ignored. bit3: usbrst: reset detect writing ?1? to this bit forces an asynchronous us b0 reset. reading this bit provides bus reset status information. read: 0: reset signaling is not present on the bus. 1: reset signaling detected on the bus. bit2: resume: force resume software can force resume signaling on the bus to wake usb0 from suspend mode. writing a ?1? to this bit while in suspend mode (susmd = ?1?) forces usb0 to generate resume sig- naling on the bus (a remote wakeup event). software should write resume = ?0? after 10 ms to15 ms to end the resume signaling. an interrupt is generated, and hardware clears susmd, when software writes resume = ?0?. bit1: susmd: suspend mode set to ?1? by hardware when usb0 enters suspend mode. cleared by hardware when soft- ware writes resume = ?0? (fo llowing a remote wakeup) or reads the cmint register after detection of resume signaling on the bus. 0: usb0 not in suspend mode. 1: usb0 in suspend mode. bit0: susen: suspend detection enable 0: suspend detection disabled. usb0 will ignore suspend signaling on the bus. 1: suspend detection en abled. usb0 will enter suspend mode if it detects suspend signaling on the bus. r/w r/w r/w r/w r/w r/w r r/w reset value isoud - - usbinh usbrst resume susmd susen 00010000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x01
c8051f320/1 152 rev. 1.4 usb register definition 15.9. framel: usb0 frame number low usb register definition 15.10. frameh: usb0 frame number high 15.8. interrupts the read-only usb0 interrupt flags are located in the usb registers shown in figure 15.11 through figure 15.13 . the associated interrupt enable bits are located in the usb registers shown in figure 15.14 through figure 15.16 . a usb0 interrupt is generated when any of the u sb interrupt flags is set to ?1?. the usb0 interrupt is enabled via the eie1 sfr (see section ?9.3. interrupt handler? on page 87 ). note: reading a usb interrupt flag register rese ts all flags in that register to ?0?. bits7-0: frame number low this register contains bits7-0 of the last received frame number. rrrrrrrrr e s e t v a l u e frame number low 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x0c bits7-3: unused. read = 0. write = don?t care. bits2-0: frame number high byte this register contains bits10-8 of the last received frame number. rrrrrrrrr e s e t v a l u e - - - - - frame number high 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x0d
rev. 1.4 153 c8051f320/1 usb register definition 15.11. in1int: usb0 in endpoint interrupt bits7?4: unused. read = 0000b. write = don?t care. bit3: in3: in endpoint 3 interrupt-pending flag this bit is cleared when software reads the in1int register. 0: in endpoint 3 interrupt inactive. 1: in endpoint 3 interrupt active. bit2: in2: in endpoint 2 interrupt-pending flag this bit is cleared when software reads the in1int register. 0: in endpoint 2 interrupt inactive. 1: in endpoint 2 interrupt active. bit1: in1: in endpoint 1 interrupt-pending flag this bit is cleared when software reads the in1int register. 0: in endpoint 1 interrupt inactive. 1: in endpoint 1 interrupt active. bit0: ep0: endpoint 0 interrupt-pending flag this bit is cleared when software reads the in1int register. 0: endpoint 0 interrupt inactive. 1: endpoint 0 interrupt active. rrrrrrrrr e s e t v a l u e - - - - in3 in2 in1 ep0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x02
c8051f320/1 154 rev. 1.4 usb register definition 15.12. out1int: usb0 out end point interrupt bits7?4: unused. read = 0000b. write = don?t care. bit3: out3: out endpoint 3 interrupt-pending flag this bit is cleared when software reads the out1int register. 0: out endpoint 3 interrupt inactive. 1: out endpoint 3 interrupt active. bit2: out2: out endpoint 2 interrupt-pending flag this bit is cleared when software reads the out1int register. 0: out endpoint 2 interrupt inactive. 1: out endpoint 2 interrupt active. bit1: out1: out endpoint 1 interrupt-pending flag this bit is cleared when software reads the out1int register. 0: out endpoint 1 interrupt inactive. 1: out endpoint 1 interrupt active. bit0: unused. read = 0b ; write = don?t care. rrrrrrrrr e s e t v a l u e - - - - out3 out2 out1 - 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x04
rev. 1.4 155 c8051f320/1 usb register definition 15.13. cmint: usb0 common interrupt bits7?4: unused. read = 0000b; write = don?t care. bit3: sof: start of frame interrupt set by hardware when a sof token is received. this interrupt event is synthesized by hard- ware: an interrupt will be genera ted when hardware expects to receive a sof event, even if the actual sof signal is missed or corrupted. this bit is cleared when software reads the cmint register. 0: sof interrupt inactive. 1: sof interrupt active. bit2: rstint: reset interrupt-pending flag set by hardware when reset signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: reset interrupt inactive. 1: reset interrupt active. bit1: rsuint: resume interrupt-pending flag set by hardware when resume signaling is det ected on the bus while usb0 is in suspend mode. this bit is cleared when software reads the cmint register. 0: resume interrupt inactive. 1: resume interrupt active. bit0: susint: suspend interrupt-pending flag when suspend detection is enabled (bit susen in register power), this bit is set by hard- ware when suspend signaling is detected on the bus. this bit is cleared when software reads the cmint register. 0: suspend interrupt inactive. 1: suspend interrupt active. rrrrrrrrr e s e t v a l u e - - - - sof rstint rsuint susint 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x06
c8051f320/1 156 rev. 1.4 usb register definition 15.14. in1ie: usb0 in endpoint interrupt enable usb register definition 15.15. out1ie: usb0 out endpoint interrupt enable bits7?4: unused. read = 0000b. write = don?t care. bit3: in3e: in endpoint 3 interrupt enable 0: in endpoint 3 interrupt disabled. 1: in endpoint 3 interrupt enabled. bit2: in2e: in endpoint 2 interrupt enable 0: in endpoint 2 interrupt disabled. 1: in endpoint 2 interrupt enabled. bit1: in1e: in endpoint 1 interrupt enable 0: in endpoint 1 interrupt disabled. 1: in endpoint 1 interrupt enabled. bit0: ep0e: endpoint 0 interrupt enable 0: endpoint 0 interrupt disabled. 1: endpoint 0 interrupt enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - in3e in2e in1e ep0e 00001111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x07 bits7?4: unused. read = 0000b. write = don?t care. bit3: out3e: out endpoint 3 interrupt enable 0: out endpoint 3 interrupt disabled. 1: out endpoint 3 interrupt enabled. bit2: out2e: out endpoint 2 interrupt enable 0: out endpoint 2 interrupt disabled. 1: out endpoint 2 interrupt enabled. bit1: out1e: out endpoint 1 interrupt enable 0: out endpoint 1 interrupt disabled. 1: out endpoint 1 interrupt enabled. bit0: unused. read = 0b; write = don?t? care. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - out3e out2e out1e - 00001110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x09
rev. 1.4 157 c8051f320/1 usb register definition 15.16. cmie: usb0 common interrupt enable 15.9. the serial interface engine the serial interface engine (sie) performs all low level usb protocol tasks, interrupting the processor when data has successfully been transmitted or received. when receiv ing data, the sie will interrupt the processor when a complete data packet has been received; appropriate handshaking signals are automat - ically generated by the sie. when tr ansmitting data, the sie will interrupt the processor when a complete data packet has been transmitted and the appropriate handshake signal has been received. the sie will not interrupt the proc essor when corr upted/erroneous packets are received. 15.10. endpoint0 endpoint0 is managed through the usb register e0csr ( figure 15.17 ). the index register must be loaded with 0x00 to access the e0csr register. an endpoint0 interrupt is generated when: 1. a data packet (out or setup) has been received and loaded into the endpoint0 fifo. the oprdy bit (e0csr.0) is set to ?1? by hardware. 2. an in data packet has successfully been unloaded from the endpoint0 fifo and transmitted to the host ; inprdy is re set to ?0? by hardware. 3. an in transaction is completed (this interrupt generated during the status stage of the transac - tion). 4. hardware sets the ststl bit (e0csr.2) after a control transaction ended due to a protocol viola tion. 5. hardware sets the suend bit (e0csr.4) beca use a control transfer ended before firmware sets the dataend bit (e0csr.3). bits7?4: unused. read = 0000b; write = don?t care. bit3: sofe: start of frame interrupt enable 0: sof interrupt disabled. 1: sof interrupt enabled. bit2: rstinte: reset interrupt enable 0: reset interrupt disabled. 1: reset interrupt enabled. bit1: rsuinte: resume interrupt enable 0: resume interrupt disabled. 1: resume interrupt enabled. bit0: susinte: suspend interrupt enable 0: suspend interrupt disabled. 1: suspend interrupt enabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value - - - - sofe rstinte rsuinte susinte 00000110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x0b
c8051f320/1 158 rev. 1.4 the e0cnt register ( figure 15.18 ) holds the number of received data bytes in the endpoint0 fifo. hardware will automatically detect protocol errors and send a stal l condition in resp onse. firmware may force a stall condition to abort the current transfer. when a stall condition is generated, the ststl bit will be set to ?1? and an interrupt gen erated. the following co nditions will cause hardwa re to generate a stall condition: 1. the host sends an out token during a out data phase after the dataend bit has been set to ?1?. 2. the host sends an in token during an in data phase after the dataend bit has been set to ?1?. 3. the host sends a packet that exceeds the maximum packet size for endpoint0. 4. the host sends a non-zero length data1 packet during the status phase of an in transaction. firmware sets the sdstl bit (e0csr.5) to ?1?. 15.10.1.endpoint0 setup transactions all control transfers must begin with a setup packet. setup packets are similar to out packets, contain - ing an 8-byte data field sent by the host. any setup p acket containing a comma nd field of anything other than 8 bytes will be automatically re jected by usb0. an endpoint0 inte rrupt is generate d when the data from a setup packet is loaded into the endpoint0 fifo. software should unload the command from the endpoint0 fifo, decode the command, perform any necess ary tasks, and set the soprdy bit to indicate that it has serviced the out packet. 15.10.2.endpoint0 in transactions when a setup request is received that requires usb0 to transmit data to the host, one or more in requests will be sent by the host. for the first in tr ansaction, firmware should lo ad an in packet into the endpoint0 fifo, and set the inprdy bit (e0csr.1). an inte rrupt will be generated when an in packet is transmitted successfully. note that no interrupt will be generated if an in requ est is received before firm - ware has loaded a packet into the endpoint0 fifo . if the re quested data exceeds the maximum packet size for endpoint0 (as reported to the host), the data should be split into multiple packets; each packet should be of the maximum packet size excluding the la st (residual) packet. if the requested data is an inte - ger multiple of the maximum packet size for endpoint 0, the last data packet should be a zero-length packet signaling the end of the transfer. firmware should set the dataend bit to ?1? after loading into the endpoint0 fifo the last data packet for a transfer. upon reception of the first in token for a particular contr ol transfer, endpoint0 is said to be in transmit mode. in this mode, only in tokens should be sent by the host to en dpoint0. the suend bit (e0csr.4) is set to ?1? if a setup or out token is rece ived while endpoint0 is in transmit mode. endpoint0 will remain in transmit m ode until any of the following occur: 1. usb0 receives an endpoint0 setup or out token. 2. firmware sends a packet less than the maximum endpoint0 packet size. 3. firmware sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to ?1? when performing (2) and (3) above. the sie will transmit a nak in response to an in token if there is no pa cket ready in the in fifo (inprdy = ?0?).
rev. 1.4 159 c8051f320/1 15.10.3.endpoint0 out transactions when a setup request is received that requires the host to transmit data to usb0, one or more out requests will be sent by the host. when an out packet is successfully received by usb0, hardware will set the oprdy bit (e0csr.0) to ?1? and generate an endpoint0 interrupt. following this interrupt, firmware should unload the out packet from the endpoint0 fifo and set the soprdy bit (e0csr.6) to ?1?. if the amount of data required for the transfer exceeds the maximum packet size for endpoint0, the data will be split into multiple p ackets. if the requested data is an integer multiple of th e maximum packet size for endpoint0 (as reported to the host), the host will send a zero-length data packet signaling the end of the transfer. upon reception of the first out token for a particular co ntrol transfer, endpoint0 is said to be in receive mode. in this mode, only out tokens should be sent by the host to endpoint0. the suend bit (e0csr.4) is set to ?1? if a setup or in token is received while endpoint0 is in receive mode. endpoint0 will remain in receive mode until: 1. the sie receives a setup or in token. 2. the host sends a packet less than the maximum endpoint0 packet size. 3. the host sends a zero-length packet. firmware should set the dataend bit (e0csr.3) to ?1? when the expected amount of data has been received. the sie will transmit a sta ll condition if the host sends an out packet after the dataend bit has been set by firmware. an interr upt will be genera ted with the ststl bit (e0csr .2) set to ?1? after the stall is transmitted.
c8051f320/1 160 rev. 1.4 usb register definition 15.17. e0csr: usb0 endpoint0 control bit7: ssuend: serv iced setup end write: software should set this bit to ?1? afte r servicing a setup end (bit suend) event. hardware clears the suend bit when software writes ?1? to ssuend. read: this bit always reads ?0?. bit6: soprdy: serviced oprdy write: software should write ?1? to this bit after servicing a received endpoint0 packet. the oprdy bit will be cleared by a write of ?1? to soprdy. read: this bit always reads ?0?. bit5: sdstl: send stall software can write ?1? to this bi t to terminate the current transfer (due to an error condition, unexpected transfer request, etc. ). hardware will clear this bit to ?0? when the stall hand- shake is transmitted. bit4: suend: setup end hardware sets this read-only bit to ?1? when a control transaction ends before software has written ?1? to the dataend bit. hardware clears this bit when software writes ?1? to ssu- end. bit3: dataend: data end software should write ?1? to this bit: 1. when writing ?1? to inprdy for the last outgoing data packet. 2. when writing ?1? to inprdy for a zero-length data packet. 3. when writing ?1? to soprdy after se rvicing the last incoming data packet. this bit is automatically cleared by hardware. bit2: ststl: sent stall hardware sets this bit to ?1? after transmitting a stall handsha ke signal. this flag must be cleared by software. bit1: inprdy: in packet ready software should write ?1? to this bit after loading a data packet into the endpoint0 fifo for transmit. hardware clea rs this bit and generates an interrupt under either of the following conditions: 1. the packet is transmitted. 2. the packet is overwritten by an incoming setup packet. 3. the packet is overwritten by an incoming out packet. bit0: oprdy: out packet ready hardware sets this read-only bit and generates an interrupt when a data packet has been received. this bit is cleared only when software writes ?1? to the soprdy bit. r/w r/w r/w r r/w r/w r/w r reset value ssuend soprdy sdstl suend dataend ststl inprdy oprdy 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x11
rev. 1.4 161 c8051f320/1 usb register definition 15.18. e0cnt: usb0 end point 0 dat a count 15.11. configuring endpoints1?3 endpoints1-3 are configured and cont rolled through their own sets of the following control/status registers: in registers eincsrl and eincsrh, and out regi sters eoutcsrl and eoutcsrh. only one set of endpoint control/status registers is mapped into the usb register address space at a time, defined by the contents of the index register ( figure 15.4 ). endpoints1-3 can be configured as in, out, or both in/out (split mode) as described in section 15.5.1 . the endpoint mode (split/normal) is selected via the split bit in register eincsrh. when split = ?1?, the corresponding endpoint fifo is sp lit, and both in and out pipes are available. when split = ?0?, the corresponding endpoint functions as either in or out; th e endpoint direction is selected by the dirsel bit in register eincsrh. 15.12. controlling endpoints1?3 in endpoints1-3 in are managed via usb registers einc srl and eincsrh. all in endpoints can be used for interrupt, bulk, or isochronous transfers. isochronous (iso) mode is enabled by writing ?1? to the iso bit in register eincsrh. bulk and interrupt transfers are handled identically by hardware. an endpoint1-3 in interrupt is generated by any of the following conditions: 1. an in packet is successfully transferred to the host. 2. software writes ?1? to the flush bit (eincs rl .3) when the target fifo is not empty. 3. hardware generates a stall condition. 15.12.1.endpoints1-3 in interrupt or bulk mode when the iso bit (eincsrh.6) = ?0? the target endpoint operates in bulk or interrupt mode. once an end - point has been configured to operate in bulk/interrupt in mode (typically following an endpoint0 set_ interface command), firmware should load an in packet into the endpoint in fifo and set the inprdy bit (eincsrl.0). upon reception of an in token, hardware will tran smit the data, clear the inprdy bit, and generate an interrupt. writing ?1? to inprdy without writin g any dat a to the endpoint fifo w ill cause a zero-length packet to be transmitted upon reception of the next in token. bit7: unused. read = 0b; write = don?t care. bits6?0: e0cnt: endpoint 0 data count this 7-bit number indicates the number of received data bytes in the endpoint 0 fifo. this number is only valid while bit oprdy is a ?1?. rrrrrrrrr e s e t v a l u e - e0cnt 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x16
c8051f320/1 162 rev. 1.4 a bulk or interrupt pipe can be shut down (or halted) by writing ?1? to the sdstl bit (eincsrl.4). while sdstl = ?1?, hardware will re s pond to all in requests with a stall condition. each time hardware gener - ates a stall condition, an interr upt will be generated and the ststl bit (eincsrl.5) set to ?1?. the ststl bit must be rese t to ?0? by firmware. hardware will automatically reset inprdy to ?0? when a packet slot is open in the endpoint fifo. note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the in fifo at a time. in this case, hardware will re set inprdy to ?0? immediately after firmware loads the first packet into the fifo and sets inprdy to ?1?. an inte rrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. when firmware writes ?1? to the fcdt bit (eincsrh.3) , the dat a toggle for each in packet will be toggled continuously, regardless of the handshake received from the host. this feature is typically used by inter - rupt endpoints functioning as rate feed back communication for isochron ous endpoints. when fcdt = ?0?, the data toggle bit will only be toggle d when an ack is sent from the host in response to an in packet. 15.12.2.endpoints1-3 in isochronous mode when the iso bit (eincsrh.6) is set to ?1?, the target endpoint operates in isochronous (iso) mode. once an endpoint has been configured fo r iso in mode, the host will send one in token (dat a request) per frame; the location of data within each frame may vary. because of this, it is recommended that double buffering be enabled for iso in endpoints. hardware will automatically reset inp rdy (eincsr l.0) to ?0? when a pack et slot is open in the endpoint fifo. note that if double buffering is enabled for the target endpoint, it is possible for firmware to load two packets into the in fifo at a time . in this case, hardware will reset in prdy to ?0? immediately after firm - ware loads the first packet in to the fifo and set s inprdy to ?1?. an interrupt will not be generated in this case; an interrupt will only be generated when a data packet is transmitted. if there is not a data packet ready in the endpoint fifo when usb0 receives an in token from the host, usb0 will transmit a zero-length data packet and set the undrun bit (eincsrl.2) to ?1?. the iso update feature (see section 15.7 ) can be useful in starting a doub le b uffered iso in endpoint. if the host has already set up the iso in pipe (has b egu n transmitting in tokens) when firmware writes the first data packet to the endpoint fifo, the next in to ken may arrive and the first data packet sent before firmware has written the second (double buffered ) data packet to the fifo. the iso update feature ensures that any data packet written to the endpoint fifo will not be tran smitted during the current frame; the packet will only be sent after a sof signal has been received.
rev. 1.4 163 c8051f320/1 usb register definition 15.19. eincsrl: usb0 in end point control low byte bit7: unused. read = 0b; write = don?t care. bit6: clrdt: clear data toggle. write: software should write ?1? to this bit to reset the in en dpoint data toggle to ?0?. read: this bit always reads ?0?. bit5: ststl: sent stall hardware sets this bit to ?1? when a stall handshake signal is transmitted. the fifo is flushed, and the inprdy bit cleared. this flag must be cleared by software. bit4: sdstl: send stall. software should write ?1? to th is bit to generate a stall handshake in response to an in token. software should write ?0? to this bit to terminate the stall signal. this bit has no effect in iso mode. bit3: flush: fifo flush. writing a ?1? to this bit flushe s the next packet to be transmit ted from the in endpoint fifo. the fifo pointer is reset and the inprdy bit is cleared. if the fifo c ontains multiple pack- ets, software must write ?1? to flush for each pack et. hardware resets the flush bit to ?0? when the fifo flush is complete. bit2: undrun: data underrun. the function of this bit depends on the in endpoint mode: iso: set when a zero-length packet is sent afte r an in token is received while bit inprdy = ?0?. interrupt/bulk: set when a nak is returned in response to an in token. this bit must be cleared by software. bit1: fifone: fifo not empty. 0: the in endpoint fifo is empty. 1. the in endpoint fifo contains one or more packets. bit0: inprdy: in packet ready. software should write ?1? to th is bit after loading a data packet into the in endpoint fifo. hardware clears inprdy due to any of the following: 1. a data packet is transmitted. 2. double buffering is enabled (dbien = ?1?) and there is an open fifo packet slot. 3. if the endpoint is in isochr onous mode (iso = ?1?) and is oud = ?1?, inprdy will read ?0? until the next sof is received. an interrupt (if enabled) will be generated when hardware clears inprdy as a result of a packet being transmitted. r w r/w r/w w r/w r/w r/w reset value - clrdt ststl sdstl flush undrun fifone inprdy 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x11
c8051f320/1 164 rev. 1.4 usb register definition 15.20. eincsrh: usb0 in end point control high byte 15.13. controlling endpoints1?3 out endpoints1-3 out are managed via usb registers eoutcsrl and eoutcsrh. all out endpoints can be used for interr upt, bulk, or isochronous transfers. isochronou s (iso) mode is enabled by writing ?1? to the iso bit in register eoutcsrh. bulk and interr upt transfers are handled identically by hardware. an endpoint1-3 out interrupt may be generated by the following: 1. hardware sets the oprd y bit (ein csrl.0) to ?1?. 2. hardware generates a stall condition. 15.13.1.endpoints1-3 out interrupt or bulk mode when the iso bit (eoutcsrh.6) = ?0? the target endpoi nt operates in bulk or interrupt mode. once an endpoint has been configured to operate in bulk/int errupt out mode (typically following an endpoint0 set_interface command), hardware will set the oprdy bit (eoutcsrl.0) to ?1? and generate an interrupt upon reception of an out token and data packet. the number of bytes in the current out data packet (the packet ready to be unloaded from the fifo) is given in the eoutcnth and eoutcntl reg - isters. in response to this interrup t, fir mware should unload the data packet from the out fifo and reset the oprdy bit to ?0?. bit7: dbien: in endpoint double-buffer enable. 0: double-buffering disabled for the selected in endpoint. 1: double-buffering enabled fo r the selected in endpoint. bit6: iso: isochronous transfer enable. this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. bit5: dirsel: endpoint direction select. this bit is valid only when the sele cted fifo is not sp lit (split = ?0?). 0: endpoint direction selected as out. 1: endpoint direction selected as in. bit4: unused. read = ?0b?. write = don?t care. b i t 3 : f c d t: f o r c e d a ta to g g l e . 0: endpoint data toggle switches only when an ack is received following a data packet transmission. 1: endpoint data toggle forced to switch after every data packet is transmitted, regardless of ack reception. bit2: split: fifo split enable. when split = ?1?, the selected endpoint fifo is split. the upper half of the selected fifo is used by the in endpoint; the lower half of the selected fifo is used by the out endpoint. bits1?0: unused. read = 00b; write = don?t care. r/w r/w r/w r r/w r/w r r reset value dbien iso dirsel - fcdt split - - 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x12
rev. 1.4 165 c8051f320/1 a bulk or interrupt pipe can be shut down (or halted ) by writing ?1? to the sdstl bit (eoutcsrl.5). while sdstl = ?1?, hardware will respond to all out requests wit h a st all condition. each time hardware gen - erates a stall condition, an interr upt will be generated and the ststl bit (eou tcsrl.6) set to ?1?. the ststl bit must be rese t to ?0? by firmware. hardware will automatically set op rdy when a packet is ready in the out fifo. note that if double buff - ering is enabled for the target endpoint, it is possible fo r two packets to be ready in the out fifo at a time. in this case, hardware will set oprdy to ?1? immediately after firmware un loads the first packet and resets oprdy to ?0?. a second interrupt will be generated in this case. 15.13.2.endpoints1-3 out isochronous mode when the iso bit (eoutcsrh.6) is set to ?1?, the target endpoint operates in isochronous (iso) mode. once an endpoint has been config ured for iso out mode, the host will send exactly one data per usb frame; the location of the data packet within each frame may vary, however. because of this, it is recom - mended that double buffering be enabled for iso out endpoints. each time a data packet is received, hardware will l oad the received dat a packe t into the endpoint fifo, set the oprdy bit (eoutcsrl.0) to ?1?, and generate an interrupt (if enabled). firmware would typically use this interrupt to unload the data packet from the endpoint fifo and reset the oprdy bit to ?0?. if a data packet is received when there is no room in the end point fifo, an inte rrupt will be generated and the ovrun bit (eoutcsrl.2) set to ?1?. if usb0 re ceives an iso data packet with a crc error, the data packet will be loaded into the endpoint fifo, oprdy will be set to ?1?, an interrupt (if en abled) will be gen - erated, and the dataerr bit (eoutcsrl.3) will be set to ?1?. software should check the dataerr bit each time a data packet is unloaded from an iso out endpoint fifo.
c8051f320/1 166 rev. 1.4 usb register definition 15.21. eoutcsrl: usb0 out end point control high byte bit7: clrdt: clear data toggle write: software should write ?1? to this bit to reset the out en dpoint data toggle to ?0?. read: this bit always reads ?0?. bit6: ststl: sent stall hardware sets this bit to ?1? when a stall handshake signal is transmitted. this flag must be cleared by software. bit5: sdstl: send stall software should write ?1? to this bit to generate a stall handshake. software should write ?0? to this bit to terminate the stall sign al. this bit has no effect in iso mode. bit4: flush: fifo flush writing a ?1? to this bit flushes the next pa cket to be read from the out endpoint fifo. the fifo pointer is reset and the oprdy bit is clea red. if the fifo contai ns multiple packets, software must write ?1? to flush for each packet. hardware resets the flush bit to ?0? when the fifo flush is complete. bit3: daterr: data error in iso mode, this bit is set by hardware if a received packet has a crc or bit-stuffing error. it is cleared when software clears oprdy . this bit is only valid in iso mode. bit2: ovrun: data overrun this bit is set by hardware when an incoming data packet cannot be loaded into the out endpoint fifo. this bit is only valid in iso mode, and must be cleared by software. 0: no data overrun. 1: a data packet was lost because of a fu ll fifo since this fl ag was last cleared. bit1: fifoful: out fifo full this bit indicates the contents of the out fifo . if double buffering is enabled for the end- point (dbien = ?1?), the fifo is full when the fifo contains two packets. if dbien = ?0?, the fifo is full when the fifo contains one packet. 0: out endpoint fifo is not full. 1: out endpoint fifo is full. bit0: oprdy: out packet ready hardware sets this bit to ?1? and generates an in terrupt when a data packet is available. soft- ware should clear this bit after each data pa cket is unloaded from the out endpoint fifo. w r/w r/w w r r/w r r/w reset value clrdt ststl sdstl flush daterr ovrun fifoful oprdy 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x14
rev. 1.4 167 c8051f320/1 usb register definition 15.22. eoutcsrh: usb0 out end point control low byte usb register definition 15.23. eoutcntl: usb0 out end point count low usb register definition 15.24. eoutcnth: usb0 out end point count high bit7: dboen: double-buffer enable 0: double-buffering disabled for the selected out endpoint. 1: double-buffering enabled for the selected out endpoint. bit6: iso: isochronous transfer enable this bit enables/disables isochronous transfers on the current endpoint. 0: endpoint configured for bulk/interrupt transfers. 1: endpoint configured for isochronous transfers. bits5?0: unused. read = 000000b; write = don?t care. r/w r/w r/w r/w r r r r reset value dboen iso - - - - - - 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x15 bits7?0: eocl: out endpoint count low byte eocl holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. this nu mber is only valid while oprdy = ?1?. rrrrrrrrr e s e t v a l u e eocl 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x16 bits7?2: unused. read = 000000b. write = don?t care. bits1?0: eoch: out endpoint count high byte eoch holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in the current out endpoint fifo. this nu mber is only valid while oprdy = ?1?. rrrrrrrrr e s e t v a l u e - - - - - - e0ch 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 usb address: 0x17
c8051f320/1 168 rev. 1.4 table 15.4. usb transceiver electri cal characteristics v dd = 3.0 to 3.6v, ?40 to +85 c unless otherwise specified. parameters symbol conditions min typ max units transmitter output high voltage v oh 2.8 v output low voltage v ol 0.8 v output crossover point v crs 1.3 2.0 v output impedance z drv driving high driving low 38 38 w pull-up resistance r pu full speed (d+ pull-up) low speed (d? pull-up) 1.425 1.425 1.5 1.5 1.575 1.575 k? k? output rise time t r low speed full speed 75 4 300 20 ns output fall time t f low speed full speed 75 4 300 20 ns receiver dif ferential input sensitivity v di | (d+) ? (d?) | 0.2 v differential input com- mon mode range v cm 0.8 2.5 v input leakage current i l pullups disabled <1.0 a note: refer to the usb specification for timing diagrams and symbol definitions.
rev. 1.4 169 c8051f320/1 16. smbus the smbus i/o interface is a two-wire, bi-directional serial bus. the smbus is compliant with the system management bus specification, version 1.1, and compatible with the i 2 c serial bus. reads and writes to the interface by the system contro ller are byte oriented with the smbu s interface autonom ously controlling the serial transfer of the data. data can be transferre d at up to 1/20th of the system clock as a master or slave (this can be faster than allowed by the smbus specification, depending on the system clock used). a method of extending the clock-low duration is ava ilable to accommodate devices with different speed capabilities on the same bus. the smbus interface may operate as a master and/or sla v e, and may function on a bus with multiple mas - ters. the smbus provides control of sda (serial data), scl ( s erial clock) generation and synchronization, arbitration logic, and start/stop control and gene ration. three sfrs are associated with the smbus: smb0cf configures the sm bus; smb0cn controls the status of the smbus; and smb0dat is the data register, used for both transmitting and receiving smbus data and slave addresses. data path control smbus control logic c r o s s b a r scl filter n sda control scl control arbitration scl synchronization irq generation scl generation (master mode) sda control interrupt request port i/o smb0cn s t a a c k r q a r b l o s t a c k s i t x m o d e m a s t e r s t o 01 00 10 11 t0 overflow t1 overflow tmr2h overflow tmr2l overflow smb0cf e n s m b i n h b u s y e x t h o l d s m b t o e s m b f t e s m b c s 1 s m b c s 0 0 1 2 3 4 5 6 7 smb0dat sda filter n figure 16.1. smbus block diagram
c8051f320/1 170 rev. 1.4 16.1. supporting documents it is assumed the reader is fam iliar with or has access to th e following supporting documents: 1. the i 2 c-bus and how to use it (including specifications), ph ilips semiconductor. 2. the i 2 c-bus specification -- versio n 2.0, philips semiconductor. 3. system management bus specification -- v e rsion 1.1, sbs implementers forum. 16.2. smbus configuration figure 16.2 shows a typical smbus configuration. the smbu s sp ecification allows any recessive voltage between 3.0 v and 5.0 v; different devices on the bus may operate at different voltage levels. the bi-direc - tional scl (serial clock) and sda (serial data) lines mu st b e connected to a positive power supply voltage through a pull-up resistor or similar circuit. every devic e connected to the bus must have an open-drain or open-collector output for both the scl and sda lines, so that both are pulled high (recessive state) when the bus is free. the maximum number of devices on the bus is limited only by the requirement that the rise and fall times on the bus not exceed 300 ns and 1000 ns, respectively. vdd = 5v master device slave device 1 slave device 2 vdd = 3v vdd = 5v vdd = 3v sda scl figure 16.2. typical smbus configuration 16.3. smbus operation two types of data transfers are possible: data transfers from a master transmitter to an addressed slave receiver (write), and data transfers from an addres sed slave transmitter to a master receiver (read). the master device initiates both types of data transfer s and provides the serial clock pulses on scl. the smbus interface may operate as a master or a slave, and multiple master devices on the same bus are supported. if two or more masters attempt to initiate a data transfer simultaneously, an arbitration scheme is employed with a single master always winning the arbitr ation. note that it is not necessary to specify one device as the master in a system ; any device who transmits a star t and a slave address becomes the master for the duration of that transfer. a typical smbus transaction consists of a start cond ition fo llowed by an address byte (bits7-1: 7-bit slave address; bit0: r/w direction bit), one or more byte s of data, and a stop condition. each byte that is received (by a master or slave) must be acknow ledged (ack) with a low sda during a high scl (see figure 16.3 ). if the receiving device does not ac k, the transmitting device will read a nack (not acknowl - edge), which is a high sda during a high scl. the direction bit (r/w) occupies the least-significant bit po sitio n of the address byte. the direction bit is set to logic 1 to indicate a "read" operation and cleared to logic 0 to indicate a "write" operation.
rev. 1.4 171 c8051f320/1 all transactions are initiated by a master, with one or more addressed slave devices as the target. the master generates the start condition and then transmits the slave address and direction bit. if the trans - action is a write operation from the ma ster to the slave, the master tr ansmits the data a byte at a time waiting for an ack from the slave at the end of each byte. for read operations , the slave transmits the data waiting for an ack from the master at the end of each byte. at the end of the data transfer, the master generates a stop condition to terminate the transaction and free the bus. figure 16.3 illustrates a typical smbus transaction. sla6 sda sla5-0 r/w d7 d6-0 scl slave address + r/w data byte start ack nack stop figure 16.3. smbus transaction 16.3.1. arbitration a master may start a transfer only if the bus is free. th e bus is free after a stop condition or after the scl and sda lines remain high for a specified time (see section ?16.3.4. scl high (smbus free) timeout? on page 172 ). in the event that two or more d evices attempt to begin a transfer at the same time, an arbitra - tion scheme is employed to force one master to give u p the bus. the master devices continue transmitting until one attempts a high while the other transmits a low. since the bus is open-drain, the bus will be pulled low. the master attempting th e high will detect a low sda and lo se the arbitration. the winning master continues its transmission without interruption; the losing master becomes a slave and receives the rest of the transfer if addressed. this arbitration scheme is non-destru ctive: one device always wins, and no data is lost. 16.3.2. clock low extension smbus provides a clock synchron ization mechanism, similar to i 2 c, which allows devices with different speed capabilities to coexist on the bus. a clock-low extension is used du ring a transfer in order to allow slower slave devices to communica te with faster masters. the slave may temporarily hold the scl line low to extend the clock low period, effectively decreasing the serial clock frequency. 16.3.3. scl low timeout if the scl line is held low by a slave device on the bus, no further communication is possible. furthermore, the master cannot force the scl line high to correct th e error condition. to solve this problem, the smbus protocol specifies that devices participating in a tran sfer must detect any clock cy cle held low longer than 25 ms as a ?timeout? condition. devices that have det ected the timeout condition must reset the communi - cation no later than 10 ms after detecting the timeout condition. when the smbtoe bit in smb0cf is set, timer 3 is used to detect scl low timeouts. timer 3 is forced to r e load when scl is high, and allowed to count when scl is low. with timer 3 enabled and configured to ov er flow after 25 ms (and smbtoe set), the timer 3 interrupt service routine can be used to reset (disable a nd r e-enable) the smbus in the event of an scl low timeout.
c8051f320/1 172 rev. 1.4 16.3.4. scl high (smbus free) timeout the smbus specification stipulates that if the scl and sda lines remain high for more that 50 s, the bus is des ignated as free. when the sm bfte bit in smb0cf is set, the bu s will be considered free if scl and sda remain high for more than 10 smbus clock source periods. if the smbus is waiting to generate a master st art, the start will be generated following this timeout. note that a clock source is required for free timeout detection, even in a slave-only implementation. 16.4. using the smbus the smbus can operate in both master and slave modes. the interface provides timing and shifting con - trol for serial transfers; higher level protocol is dete rm ined by user software. the smbus interface provides the following application-independent features: ? byte-wise serial data transfers ? clock signal generation on scl (master mode only) and sda data synchronization ? timeout/bus error recognition, as define d by the smb0cf configuration register ? start/stop timing, detection, and generation ? bus arbitration ? interrupt generation ? status information smbus interrupts are generated for each data byte or slave ad dress that is transf erred. when transmitting, this interrupt is generated after the ack cycle so th at software may read the received ack value; when receiving data, this interrupt is generated before t he ack cycle so that software may define the outgoing ack value. see section ?16.5. smbus transfer modes? on page 180 for more details on transmission sequences. interrupts are also generated to indicate the beginning of a transfer when a master (start generated), or the end of a transfer when a slave (stop detected) . software should read the smb0cn (smbus control register) to find the cause of the smbus inte rrupt. the smb0cn register is described in section ?16.4.2. smb0cn control register? on page 176 ; ta b l e 16.4 provides a quick smb0cn decoding refer - ence. smbus configuration options include: ? timeout detection (scl low timeout and/or bus free timeout) ? sda setup and hold time extensions ? slave event enable/disable ? clock source selection these options are selected in the smb0cf register, as described in section ?16.4.1. smbus configuration register? on page 173 .
rev. 1.4 173 c8051f320/1 16.4.1. smbus configuration register the smbus configuration register (s mb0cf) is used to enable the smbus master and/or slave modes, select the smbus clock source, and select the smbus timing and timeout options . when the ensmb bit is set, the smbus is enabled for all master and slave events. slave events may be disabled by setting the inh bit. with slave events inhibited, the smbus in terface will still monitor the scl and sda pins; however, the interface will nack all received addresses and will not generate any slave inte rrupts. when the inh bit is set, all slave events will be inhibited following the ne xt start (interrupts will cont inue for the duration of the current transfer). table 16.1. smbus clock source selection the smbcs1-0 bits select the smbus clock source, which is used on ly when operating as a master or when the free timeout detection is enabled. when op erating as a master, overflows from the selected source determine the absolute minimum scl low and high times as defined in equation 16.1 . note that the selected clock source may be shared by other peripherals so long as the timer is left running at all times. for example, timer 1 overflows may generate the smbus and uar t baud rates simultaneously. timer configuration is covered in section ?19. timers? on page 209 . equation 16.1. minimum sc l high and low times t highmin t lowmin 1 f clocksourceoverflow ---------------------------------- ----------- - == the selected clock source should be configured to establish the minimum scl high and low times as per equation 16.1 . when the interface is operating as a master ( a nd scl is not driven or extended by any other devices on the bus), the typica l smbus bit rate is app ro ximated by equation 16.2 . equation 16.2. typi cal smbus bit rate bitrate f clocksourceoverflow 3 --------------- ------------------------------ - = smbcs 1 smbcs 0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow
c8051f320/1 174 rev. 1.4 figure 16.4 shows the typical scl generation described by equation 16.2 . notice that t high is typically twice as large as t low . the actual scl output may vary due to other devices on the bus (scl may be extended low by slower slave devices, or driven low by contending master devices). the bit rate when operating as a master will never exce ed the limits defined by equation equation 16.1 . scl timer source overflows scl high timeout t low t high figure 16.4. typical smbus scl generation setting the exthold bit extends the minimum setup and hold times for the sda line. the minimum sda setup time defines the absolute mini mum time that sda is stable before scl transitions from low-to-high. the minimum sda hold time defines the absolute minimum time that the current sda value remains stable after scl transitions from high-to-low. exthold should be set so that the minimum setup and hold times meet the smbus specification requirements of 250 ns and 300 ns, respectively. ta b l e 16.2 shows the min - imum setup and hold times for the two exthold settings. setup and hold time extensions are typically necessary when sysclk is above 10 mh z. table 16.2. minimum sda setup and hold times *note: setup time for ack bit transmissions and the msb of all data transfers. the s/w delay occurs between the time smb0dat or ack is written and when si is cleared. note that if si is cleared in the same wr ite that defines the ou tgoing ack value, s/w delay is zero. with the smbtoe bit set, timer 3 should be configured to overflow after 25 ms in order to detect scl low timeout s (see section ?16.3.3. scl low timeout? on page 171 ). the smbus interface will force timer 3 to reload while scl is high, and allow timer 3 to count when scl is low. the timer 3 interrupt service routine sho u ld be used to reset smbus communication by disabling and re-enabling the smbus. smbus free timeout detection can be enabled by setting the smbfte bit. when this bit is s e t, the bus will be considered free if sda and scl remain high for more than 10 smbus clock source periods (see figure 16.4 ). when a free timeout is dete cted, the interface will res p ond as if a stop was detected (an interrupt will be generat ed, and st o will be set). exthold minimum sda setup time minimum sda hold time 0 t low - 4 system clocks or 1 system clock + s/w delay* 3 system clocks 1 11 system clocks 12 system clocks
rev. 1.4 175 c8051f320/1 sfr definition 16.1. bit7: ensmb: smbus enable. this bit enables/disables the smbus interface. when enabled, the interface constantly mon- itors the sda and scl pins. 0: smbus interface disabled. 1: smbus interface enabled. bit6: inh: smbus slave inhibit. when this bit is set to logic 1, the smbus does not generate an interrupt when slave events occur. this effectively removes the smbus slave from the bus. master mode interrupts are not affected. 0: smbus slave mode enabled. 1: smbus slave mode inhibited. bit5: busy: smbus busy indicator. this bit is set to logic 1 by hardware when a transfer is in progress. it is cleared to logic 0 when a stop or free-timeout is sensed. bit4: exthold: smbus setup and hold time extension enable. this bit controls the sda setup and hold times according to . 0: sda extended setup and hold times disabled. 1: sda extended setup and hold times enabled. bit3: smbtoe: smbus scl timeout detection enable. this bit enables scl low timeout detection. if set to logic 1, the smbus forces timer 3 to reload while scl is high and allows timer 3 to count when scl goes low. timer 3 should be programmed to generate interrupts at 25 ms, and the timer 3 interrupt service routine should reset smbus communication. bit2: smbfte: smbus free ti meout detection enable. when this bit is set to logic 1, the bus will be considered free if scl and sda remain high for more than 10 smbus clock source periods. bits1?0: smbcs1?smbcs0: smbus clock source selection. these two bits select the smbus clock sour ce, which is used to generate the smbus bit rate. the selected device should be configured according to equation 16.1. r/w r/w r r/w r/w r/w r/w r/w reset value ensmb inh busy exthold smbtoe smbfte smbcs1 smbcs0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc1 smbcs1 smbcs0 smbus clock source 0 0 timer 0 overflow 0 1 timer 1 overflow 1 0 timer 2 high byte overflow 1 1 timer 2 low byte overflow smb0cf: smbus clock/configuration
c8051f320/1 176 rev. 1.4 16.4.2. smb0cn control register smb0cn is used to control the interface and to provide status information (see figure 16.2 ). the higher four bits of smb0cn (master, txmode, sta, and sto) fo rm a status vector that can be used to jump to service routines. master and txmode indicate the master/slave state and transmit/receive modes, respectively. sta and sto indicate that a start and/or stop ha s been detected or generated since the last smbus interrupt. sta and sto are also used to generate start and stop conditions when operating as a mas - ter. writing a ?1? to sta will cause the smbus interfac e to enter mas ter mode and generate a start when the bus becomes free (sta is not cleared by hardware after the start is generated). writing a ?1? to sto while in master mode will cause the interface to generate a stop and end the current transfer after the next ack cycle. if sto and sta are both set (while in master mode), a stop followed by a start will be generated. as a receiver, writing the ack bit defines the outgoing ack value; as a transmitter, reading the ack bit indicates the value received on the last ack cycle. ackrq is set each time a byte is received, indicating that an outgoing ack value is needed. when ackrq is set, software should write the desired outgoing value to the ack bit before clearing si. a nack will be generated if so ftware does not write the ack bit before clearing si. sda will reflec t the defined ack value immediately following a write to the ack bit; however scl will remain low un til si is cleared. if a received slave address is not acknowledged, further slave events will be ignored unt il the next start is detected. the arblost bit indicates that the interface has lost an arbitration. this may occur anytime the interface is transmitting (master or slave). a lost arbitratio n while operating as a slave indicates a bus error condi - tion. arblost is cleared by hardware each time si is cleared. the si bit (smbus interrupt flag) is set at the beginning and end of each transfer, after each byte frame, or when an arbitration is lost; see ta b l e 16.3 for more details. important note about the si bit: the smbus interface is stalled while si is set; thus scl is held low, and the bus is stalled until software clears si. ta b l e 16.3 lists all sources for hardware changes to the smb0cn bits. refer to ta b l e 16.4 for smbus sta - tus decoding using the smb0cn register.
rev. 1.4 177 c8051f320/1 sfr definition 16.2. bit7: master: smbus master/slave indicator. this read-only bit indicates when the smbus is operating as a master. 0: smbus operating in slave mode. 1: smbus operating in master mode. bit6: txmode: smbus tran smit mode indicator. this read-only bit indicates when the smbus is operating as a transmitter. 0: smbus in receiver mode. 1: smbus in transmitter mode. bit5: sta: smbus start flag. write: 0: no start generated. 1: when operating as a master, a start condition is transmitted if the bus is free (if the bus is not free, the start is transmitted after a stop is received or a time out is detected). if sta is set by software as an active master , a repeated start will be generated after the next ack cycle. read: 0: no start or repeated start detected. 1: start or repeated start detected. bit4: sto: smbus stop flag. write: 0: no stop condition is transmitted. 1: setting sto to logic 1 causes a stop co ndition to be transmitted after the next ack cycle. when the stop condition is generated, hardware clears sto to logic 0. if both sta and sto are set, a stop condition is transmitted followed by a start condition. read: 0: no stop condition detected. 1: stop condition detected (if in slave mode) or pending (if in master mode). bit3: ackrq: smbus acknowledge request this read-only bit is set to logic 1 when the smbus has received a byte and needs the ack bit to be written with the correct ack response value. bit2: arblost: smbus arbitration lost indicator. this read-only bit is set to logic 1 when the smbus loses arbitration while operating as a transmitter. a lost arbitration while a slave indicates a bus error condition. bit1: ack: smbus acknowledge flag. this bit defines the out-going ack level and re cords incoming ack levels. it should be writ- ten each time a byte is received (when ackr q=1), or read after each byte is transmitted. 0: a "not acknowledge" has been received (i f in transmitter mode) or will be transmitted (if in receiver mode). 1: an "acknowledge" has been re ceived (if in transmitter mode ) or will be transmitted (if in receiver mode). bit0: si: smbus interrupt flag. this bit is set by hardware under the conditions listed in table 16.3. si must be cleared by software. while si is set, scl is held low and the smbus is stalled. r r r/w r/w r r r/w r/w reset value master txmode sta sto ackrq arblost ack si 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xc0 smb0cn: smbus control
table 16.3. sources for hardware changes to smb0cn ? a start is generated. ? a stop is generated. ? arbitration is lost. ? start is generated. ? smb0d at is written before the start of an smbus frame. ? a st art is detected. ? arbitration is lost. ? smb0da t is not written before the st art of an smbus frame. ? a st art followed by an address byte is re ceived. ? must be cleared by software. ? a st op is detected while addressed as a slave. ? ar bitration is lost due to a detected stop. ? a pen ding stop is generated. ? a byte has be en r eceived and an ack response value is needed. ? after each ack cycle. ? a re peated start is detected as a master when sta is low (unwanted repeated start). ? scl is sensed low while attempt ing to gener - ate a stop or repeated start condition. ? sda is sensed low wh ile transmitting a ?1? (e xcluding ack bits). ? each time si is cleared. ? the incoming ack value is low (acknowl - edge). ? the incoming ack value is high (not acknowledge). ? a st art has been generated. ? l ost arbitration. ? a byte has be en tra nsmitted and an ack/nack received. ? a byte has be en r eceived. ? a st art or repeated start followed by a slave add ress + r/w has been received. ? a st op has been received. ? mu st be cleared by software. c8051f320/1 178 rev. 1.4 bit set by hardware when: cleared by hardware when: master txmode sta sto ackrq arblost ack si
rev. 1.4 179 c8051f320/1 16.4.3. data register the smbus data register smb0dat holds a byte of serial data to be transmitted or one that has just been received. software may safely read or write to the data register when the si flag is set. software should not attempt to access the smb0dat register when the smbus is enabled and the si flag is cleared to logic 0, a s the interface may be in the process of shifting a byte of data into or out of the register. data in smb0dat is always shifted ou t msb first. af ter a byte has been received, the first bit of received data is located at the msb of smb0dat. while data is being shifted out, data on the bus is simultaneously being shifted in. smb0dat always contains the last data byte present on the bus. in the event of lost arbi - tration, the transition from master transmitter to slave r e ceiver is made with the correct data or address in smb0dat. sfr definition 16.3. bits7?0: smb0dat: smbus data. the smb0dat register contains a byte of data to be transmitted on the smbus serial inter- face or a byte that has just been received on the smbus serial interface. the cpu can read from or write to this register whenever the si serial interrupt flag (smb0cn.0) is set to logic 1. the serial data in the register remains stable as long as the si flag is set. when the si flag is not set, the system may be in the process of shifting data in/out and the cpu should not atte mpt to access this register. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xc2 smb0dat: smbus data
c8051f320/1 180 rev. 1.4 16.5. smbus transfer modes the smbus interface may be configured to operate as master and/or slave. at any particular time, it will be operating in one of the following four modes: master transmitter, master receiver, slave transmitter, or slave receiver. the smbus interface enters master mo de any time a start is generated, and remains in master mode until it loses an arbitration or generates a stop. an smbus interrupt is generated at the end of all smbus byte frames; however, note that the inte rrupt is generated before the ack cycle when operat - ing as a receiver, and after the ack cycle when operating as a transmitter. 16.5.1. master transmitter mode serial data is transmitted on sda while the serial cl ock is output on scl. the smbus interface generates the start condition and transmits the first byte cont aining the address of the target slave and the data direction bit. in this case the da ta direction bit (r/w) will be logic 0 (write). the master then transmits o ne o r more bytes of serial data. after each byte is transmitted, an acknowled ge bit is generated by the slave. the transfer is en ded when the sto bit is set and a stop is generated. note that the interface will switch to master receiver mode if smb0dat is not written follo wing a master transmitter interrupt. figure 16.5 shows a typical master transmitter sequence. two transmit data bytes are shown, though any number of bytes may be transmitted. notice that the ?data byte transferred? interrupts occur af te r the ack cycle in this mode. a a a s w p data byte data byte sla s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 16.5. typical mast er transmitter sequence
rev. 1.4 181 c8051f320/1 16.5.2. master receiver mode serial data is received on sda while the serial clock is output on scl. the smbus interface generates the start condition and transmits the first byte containing the address of the target slave and the data direc - tion bit. in this case the dat a direction bit (r/w) will be logic 1 (read). serial data is then received from the slave on sda while the smbus outputs the serial clock. the slave transmits one or more bytes of serial data. after each byte is received, ackrq is set to ?1? and an interrupt is generated. software must write the ack bit (smb0cn.1) to define the outgoing ackno wledge value (note: writing a ?1? to the ack bit gen - erates an ack; writing a ?0? genera tes a nack). sof t ware should write a ?0? to the ack bit after the last byte is received, to transmit a na ck. the interface exits master receiver mode after the sto bit is set and a stop is generated. note that the interface will switch to master tr ansmitter mode if smb0dat is written while an active master receiver. figure 16.6 shows a typical master rece iv er sequence. two received data bytes are shown, though any number of bytes may be r eceived. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. data byte data byte a n a s r p sla s = start p = stop a = ack n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 16.6. typical m aster receiver sequence
c8051f320/1 182 rev. 1.4 16.5.3. slave receiver mode serial data is received on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode when a start followed by a slave address and direction bit (write in this case) is received. upon entering slave receiver mode, an interrupt is generated and the ackrq bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the rece ived slave address is ignored, slav e interrupts will be inhibited until the next start is detected. if the received slave addr ess is acknowledged, zero or more data bytes are received. software must write the ack bit after each received byte to ack or nack the received byte. the interface exits slave receiver mode after receiving a stop. note that the interface will switch to slave transmitter mode if smb0 dat is written while an active slave receiver. figure 16.7 shows a typical slave receiver sequence. two received data bytes are shown, tho u gh any number of bytes may be received. notice that the ?data byte transferred? interrupts occur before the ack cycle in this mode. p w sla s data byte data byte a a a s = start p = stop a = ack w = write sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 16.7. typical sl ave receiver sequence
rev. 1.4 183 c8051f320/1 16.5.4. slave transmitter mode serial data is transmitted on sda and the clock is re ceived on scl. when slave events are enabled (inh = 0), the interface enters slave receiver mode (to re ceive the slave address) when a start followed by a slave address and direction bit (read in this case) is received. upon entering slave transmitter mode, an interrupt is generated and the ackr q bit is set. software responds to the received slave address with an ack, or ignores the received slave address with a nack. if the received slave address is ignored, slave interrupts will be inhibited un til a start is detected. if the received slave address is acknowledged, data should be written to smb0dat to be transmitted. the interface enters slave transmitter mode, and trans - mits one or more bytes of data. after each byte is tr an smitte d, the master sends an acknowledge bit; if the acknowledge bit is an ack, smb0dat should be writt en with the next data byte. if the acknowledge bit is a nack, smb0dat should not be written to before si is cleared (note: an error condition may be gener - ated if smb0dat is written following a received nack whi l e in slave transmitter mode). the interface exits slave transmitter mode after receiving a stop. note that the interface will sw itch to slave receiver mode if smb0dat is not written fo llowing a slave tran smitter interrupt. figure 16.8 shows a typical slave transmitter sequence. two transmitted data bytes ar e shown , though any number of bytes may be trans - mitted. notice that the ?data byte tr an sferred? interrupts occur after the ack cycle in this mode. p r sla s data byte data byte a n a s = start p = stop n = nack r = read sla = slave address received by smbus interface transmitted by smbus interface interrupt interrupt interrupt interrupt figure 16.8. typical sl ave transmitter sequence
c8051f320/1 184 rev. 1.4 16.6. smbus status decoding the current smbus status can be easily decoded using the smb0cn register. in the table below, status vector refers to the four upper bits of smb0cn : master, txmode, sta, and sto. note that the shown response options are only the typical response s; application-specific pr ocedures are allowed as long as they conform to the smbus specification. hig hlighted responses are allowed but do not conform to the smbus specification. table 16.4. smbus status decoding mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack master transmitter 1110 0 0 x a master start was generated. load slave address + r/w into smb0da t. 0 0 x 1100 000 a master data or address byte was trans mitted; nack received. set sta to restart transfer. 1 0 x abort transfer. 0 1 x 001 a master data or address byte was trans mitted; ack received. load next data byte into smb0da t. 0 0 x end transfer with stop. 0 1 x end transfer with stop and st art another transfer. 1 1 x send repeated start. 1 0 x switch to master receiver mode (clear si without writ - ing new data to smb0dat). 0 0 x
rev. 1.4 185 c8051f320/1 master receiver 1000 1 0 x a master data byte was received; ack requested. acknowledge received byte; read smb0da t. 0 0 1 send nack to indicate last b yte, and send stop. 0 1 0 send nack to indicate last byte, and send stop fol - lowed by start. 1 1 0 send ack followed by re peated start. 1 0 1 send nack to indicate last byte, a nd send repeated start. 1 0 0 send ack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 1 send nack and switch to master transmitter mode (write to smb0dat before clearing si). 0 0 0 slave transmitter 0100 000 a slave byte was transmitted; nac k received. no action required (expect - ing stop condition). 0 0 x 001 a slave byte was transmitted; ack received. load smb0dat with next dat a byte to transmit. 0 0 x 01x a slave byte was transmitted; er ror detected. no action required (expect - ing master to end transfer). 0 0 x 0101 0 x x an illegal stop or bus error was de tected while a slave transmis - sion was in progress. clear sto. 0 0 x table 16.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
c8051f320/1 186 rev. 1.4 slave receiver 0010 10x a slave address was received; ack requested. acknowledge received ad dress. 0 0 1 do not acknowledge re ceived address. 0 0 0 11x lost arbitration as master; slave ad dress received; ack requested. acknowledge received ad dress. 0 0 1 do not acknowledge re ceived address. 0 0 0 reschedule failed transfer; do not acknowledge received address. 1 0 0 0010 0 1 x lost arbitration while attempting a r epeated start. abort failed transfer. 0 0 x reschedule failed transfer. 1 0 x 0001 11 x lost arbitration while attempting a st op. no action required (transfer comp lete/aborted). 0 0 0 00x a stop was detected while ad dressed as a slave transmitter or slave receiver. clear sto. 0 0 x 01x lost arbitration due to a detected st op. abort transfer. 0 0 x reschedule failed transfer. 1 0 x 0000 10 x a slave byte was received; ack r equested. acknowledge received byte; read smb0da t. 0 0 1 do not acknowledge re ceived byte. 0 0 0 11x lost arbitration while transmitting a da ta byte as master. abort failed transfer. 0 0 0 reschedule failed transfer. 1 0 0 table 16.4. smbus status decoding (continued) mode values read current smbus state typical response options values written status vector ackrq arblost ack sta sto ack
rev. 1.4 187 c8051f320/1 17. uart0 uart0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 uart. enha nced baud rate support allows a wide range of clock sources to generate standard baud rates (details in section ?17.1. enhanced baud rate generation? on page 188 ). received data buffering allows uart0 to start reception of a second incoming data byte be fore software has finished reading the previous data byte. uart0 has two associated sfrs: serial control regist er 0 (scon0) and serial data buffer 0 (sbuf0). the single sbuf0 location provides access to both transmit and receive registers. writes to sbuf0 always access the transmit register. reads of sbuf0 always access the buffered receive register; it is not possible to read data from the transmit register. with uart0 interrupts enabled, an interrupt is generate d each time a transmit is completed (ti0 is set in scon0), or a data byte has been received (ri0 is set in scon0). the uart 0 interrupt flags are not cleared by hardware when the cpu vectors to the interr upt service routine. they must be cleared manually by software, allowing software to determine the cause of the uart0 interrupt (transmit complete or receive complete). uart baud rate generator ri scon ri ti rb8 tb8 ren mce smode tx control tx clock send sbuf (tx shift) start data write to sbuf crossbar tx shift zero detector tx irq set qd clr stop bit tb8 sfr bus serial port interrupt ti port i/o rx control start rx clock load sbuf shift 0x1ff rb8 rx irq input shift register (9 bits) load sbuf read sbuf sfr bus crossbar rx sbuf (rx latch) figure 17.1. uart0 block diagram
c8051f320/1 188 rev. 1.4 17.1. enhanced baud rate generation the uart0 baud rate is generated by timer 1 in 8-bit auto-reload mode. the tx clock is generated by tl1; the rx clock is generated by a copy of tl1 (shown as rx timer in figure 17.2 ), which is not user- accessible. both tx and rx timer overflows are divid ed by two to generate the tx and rx baud rates. the rx timer runs when timer 1 is enabled, and uses the same reload value (th1). however, an rx timer reload is forced when a start condition is de te ct ed on the rx pin. th is allows a receive to begin any time a start is detected, independent of the tx timer state. rx timer start detected overflow overflow th1 tl1 tx clock 2 rx clock 2 timer 1 uart figure 17.2. uart0 baud rate logic timer 1 should be configured for mode 2, 8-bit auto-reload (see section ?19.1.3. mode 2: 8-bit coun - ter/timer with auto-reload? on page 211 ). the timer 1 reload value should be set so that overflows will occur at two times the desired uart b aud rate fr equ ency. note that timer 1 may be clocked by one of six sources: sysclk, sysclk / 4, sysclk / 12, sysclk / 48, the external oscillator clock / 8, or an exter - nal input t1. for any given timer 1 clock source, the uart0 baud rate is determined by equation 17.1 . equation 17.1. uart0 baud rate uartbaudrate t 1 clk 256 t 1 h ? ?? ------------------------------ - 1 2 -- - ? = wher e t1 clk is the frequency of the clock supplied to timer 1, and t1h is the high byte of timer 1 (reload value). timer 1 clock frequency is selected as described in section ?19. timers? on page 209 . a quick ref - erence for typical baud rates and sy stem clock frequencies is given in ta b l e 17.1 . note that the internal oscillator may still generate the system clock wh en the ex ternal osc illator is driving timer 1. 17.2. operational modes uart0 provides standard asynchronous, full duplex communication. the uart mode (8-bit or 9-bit) is selected by the s0mode bit (scon0.7). typical uart connection options are shown below.
or rs-232 c8051fxxx rs-232 level xltr tx rx c8051fxxx rx tx mcu rx tx 8-bit uart mode uses a total of 10 bits per data byte: one start bit, eight data bits (lsb first), and one stop bit. data are transmitted lsb first from the tx0 pin a nd received at the rx0 pin. on receive, the eight data bits are stored in sbuf0 and the stop bit goes into rb80 (scon0.2). data transmission begins wh en s o ftware writes a data byte to th e sbuf0 register. the ti0 transmit inter - rupt flag (scon0.1) is set at the end of the transmi ssion ( t he beginning of the stop-bit time). data recep - tion can begin any time after the ren0 rece ive enable bit (scon0.4) is set to logic 1. after the stop bit is received, the data byte w ill be loaded into the sbuf0 re ceive register if the follo wing conditions are met: ri0 must be logic 0, and if mce0 is logic 1, the stop bit must be logic 1. in the event of a receive data over - run, the first received 8 bits are latched into the sbuf0 receive register and the following overrun data bits ar e lost. if these conditions are met, the eight bits of data is stor ed in sbuf0, the stop bit is stored in rb80 and the ri0 flag is set. if these conditio ns are not met, sbuf0 and rb80 will no t be loaded and the ri0 flag will not be set. an interrupt will occur if enabled when ei ther ti0 or ri0 is set. d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space rev. 1.4 189 c8051f320/1 figure 17.3. uart interconnect diagram 17.2.1. 8-bit uart figure 17.4. 8-bit u art timing diagram
c8051f320/1 190 rev. 1.4 17.2.2. 9-bit uart 9-bit uart mode uses a total of eleven bits per data byte: a start bit, 8 data bits (lsb first), a programma - ble ninth data bit, and a stop bit. the state of the nint h transmit dat a bit is determ ined by the value in tb80 (scon0.3), which is assigned by user software. it can be assigned the value of the parity flag (bit p in reg - ister psw) for error detection, or used in multiprocessor communications. on receive, the ninth data bit g oes into rb80 (scon0.2) and the stop bit is ignored. data transmission begins when an instruction writes a d ata byte to the sbuf0 register. the ti0 transmit interrupt flag (scon0.1) is set at the end of the tran smission (the beginning of the stop-bit time). data reception can begin any time after the ren0 receive en able bit (scon0.4) is set to ?1?. after the stop bit is received, the data byte will be lo aded into the sbuf0 receive register if the followin g conditions are met: (1) ri0 must be logic 0, and (2) if mce0 is logic 1, the 9th bit must be logic 1 (when mce0 is logic 0, the st ate of the ninth data bit is unimportant). if these cond itions are met, the eight bits of data are stored in sbuf0, the ninth bit is stored in rb80, and the ri0 flag is set to ?1?. if the above conditions are not met, sbuf0 and rb80 will not be loaded and the ri0 flag will not be set to ?1?. a ua rt0 interrupt will occur if enabled when either ti0 or ri0 is set to ?1?. figure 17.5. 9-bit u art timing diagram 17.3. multiprocessor communications 9-bit uart mode supports multiprocessor communication between a master processor and one or more slave processors by special use of t he ninth data bit. when a master processor wants to transmit to one or more slaves, it first sends an address byte to select th e target(s). an address byte differs from a data byte in that its ninth bit is logic 1; in a data byte, the ninth bit is always set to logic 0. setting the mce0 bit (scon0.5) of a slave processor co n figures its uart such that when a stop bit is received, the uart will gener ate an interrupt only if the ninth bit is logic 1 (rb80 = 1) signifying an address by te has been received. in the uart interrupt handler, software will compare the received address with the slave's own assigned 8-bit addre ss. if the addresses match, the slav e will clear its mce0 bit to enable interrupts on the reception of the following data byte (s). slaves that weren't addressed leave their mce0 bits set and do not generate interrupts on the reception of the following data bytes, thereby ignoring the data. once the entire message is received, the addres sed slave resets its mce0 bit to ignore all transmis - sions until it receives the next address byte. multiple addresses can be assigned to a single sl ave and /or a single address can be assigned to multiple slaves, thereby enabling "broadcast" transmissions to more than one slave simultaneously. the master processor can be configured to receive all transmissi ons or a protocol can be implemented such that the master/slave role is tem porarily reversed to enable half-duplex transmission between the original master and slave(s). d1 d0 d2 d3 d4 d5 d6 d7 start bit mark stop bit bit times bit sampling space d8
rev. 1.4 191 c8051f320/1 figure 17.6. uart multi-processor mode interconnect diagram master device slave device tx rx rx tx slave device rx tx slave device rx tx v+
c8051f320/1 192 rev. 1.4 sfr definition 17.1. scon0: serial port 0 control bit7: s0mode: serial port 0 operation mode. this bit selects the uart0 operation mode. 0: 8-bit uart with variable baud rate. 1: 9-bit uart with variable baud rate. bit6: unused. read = 1b. write = don?t care. bit5: mce0: multiprocesso r communication enable. the function of this bit is dependent on the serial port 0 operation mode. s0mode = 0: checks for valid stop bit. 0: logic level of stop bit is ignored. 1: ri0 will only be activated if stop bit is logic level 1. s0mode = 1: multiprocess or communications enable. 0: logic level of ninth bit is ignored. 1: ri0 is set and an interrupt is genera ted only when the ninth bit is logic 1. bit4: ren0: receive enable. this bit enables/disables the uart receiver. 0: uart0 reception disabled. 1: uart0 reception enabled. bit3: tb80: ninth transmission bit. the logic level of this bit will be assigned to the ninth transmis sion bit in 9-bit uart mode. it is not used in 8-bit uart mode. set or cleared by software as required. bit2: rb80: ninth receive bit. rb80 is assigned the value of the stop bit in mode 0; it is assigned the value of the 9th data bit in mode 1. bit1: ti0: transmit interrupt flag. set by hardware when a byte of data has been transmitted by uart0 (after the 8th bit in 8- bit uart mode, or at the beginning of the stop bit in 9-bit uart mode). when the uart0 interrupt is enabled, setting th is bit causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by software. bit0: ri0: receive interrupt flag. set to ?1? by hardware when a byte of data has been received by uart0 (set at the stop bit sampling time). when the uart0 interrupt is enabl ed, setting this bit to ?1? causes the cpu to vector to the uart0 interrupt service routine. this bit must be cleared manually by soft- ware. r/w r r/w r/w r/w r/w r/w r/w reset value s0mode - mce0 ren0 tb80 rb80 ti0 ri0 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0x98
rev. 1.4 193 c8051f320/1 sfr definition 17.2. sbuf0: serial (uart0 ) por t data buffer bits7?0: sbuf0[7:0]: serial data buffer bits 7?0 (msb-lsb) this sfr accesses two registers; a transmit sh ift register and a receive latch register. when data is written to sbuf0, it goes to the transmit shift register and is held for serial transmis- sion. writing a byte to sbuf0 initiates the transmission. a r ead of sbuf0 returns the con- tents of the receive latch. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x99
c8051f320/1 194 rev. 1.4 table 17.1. timer settings for standard baud rates using the in ternal oscillator target baud rate (bps) actual baud rate (bps) baud rate error oscillator divide factor timer clock source sca1-sca0 (pre-scale select)* t1m* timer 1 reload value (hex) sysclk = 12 mhz 230400 23076 9 0.16% 52 sysclk xx 1 0xe6 115200 115385 0.16% 104 sysclk xx 1 0xcc 57600 57692 0.16% 20 8 sysclk xx 1 0x98 28800 28846 0.16% 41 6 sysclk xx 1 0x30 14400 14423 0.16% 832 sysclk / 4 01 0 0x98 9600 9615 0.16% 1248 sysclk / 4 01 0 0x64 2400 2404 0.16% 4992 sysclk / 12 00 0 0x30 1200 1202 0.16% 9984 sysclk / 48 10 0 0x98 sysclk = 24 mhz 230400 230769 0 .16% 104 sysclk xx 1 0xcc 115200 115385 0.16% 208 sysclk xx 1 0x98 57600 57692 0.16% 41 6 sysclk xx 1 0x30 28800 28846 0.16% 832 sysclk / 4 01 0 0x98 14400 14423 0.16% 1664 sysclk / 4 01 0 0x30 9600 9615 0.16% 2496 sysclk / 12 00 0 0x98 2400 2404 0.16% 9984 sysclk / 48 10 0 0x98 1200 1202 0.16% 19968 sysclk / 48 10 0 0x30 x = don?t care *note: sca1-sca0 and t1m define the timer clock source. bit definitions for these values can be found in section ?19.1. timer 0 and timer 1? on page 209 .
rev. 1.4 195 c8051f320/1 18. enhanced serial peri pheral interface (spi0) the enhanced serial peripheral interface (spi0) prov ides access to a flexible, full-duplex synchronous serial bus. spi0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul - tiple masters and slaves on a single spi b u s. the slave-select (nss) signal can be configured as an input to select spi0 in slave mode, or to disable master mode operation in a multi-master environment, avoiding contention on the spi bus when more than one master attempts simultaneous data transfers. nss can also be configured as a chip-select output in master mode, or disabled for 3-wire operation. additional gen - eral purpose port i/o pins can be used to se lec t multiple slave dev ices in master mode. sfr bus data path control sfr bus write spi0dat receive data buffer spi0dat 0 1 2 3 4 5 6 7 shift register spi control logic spi0ckr scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 spi0cfg spi0cn pin interface control pin control logic c r o s s b a r port i/o read spi0dat spi irq tx data rx data sck mosi miso nss transmit data buffer clock divide logic sysclk ckpha ckpol slvsel nssmd1 nssmd0 spibsy msten nssin srmt rxbmt spif wcol modf rxovrn txbmt spien figure 18.1. spi block diagram
c8051f320/1 196 rev. 1.4 18.1. signal descriptions the four signals used by spi0 (mosi, miso, sck, nss) are described below. 18.1.1. master out, slave in (mosi) the master-out, slave-in (mosi) signal is an output fr om a master device and an input to slave devices. it is used to serially transfer data from the master to th e slave. this signal is an output when spi0 is operat - ing as a master and an input when spi0 is operating as a slave. data is transferred most-significant bit first. when configured as a master, mosi is driven by the msb of the shift register in both 3- and 4-wire mode. 18.1.2. master in, slave out (miso) the master-in, slave-out (miso) signal is an output from a slave device and an input to the master device. it is used to serially transfer data from the slave to the master. this signal is an input when spi0 is operat - ing as a master and an output when spi0 is operating a s a slave. data is transferred most-significant bit first. the miso pin is placed in a high-impedance stat e when the spi module is disabled and when the spi operates in 4-wire mode as a slave that is not select ed. when acting as a slave in 3-wire mode, miso is always driven by the msb of the shift register. 18.1.3. serial clock (sck) the serial clock (sck) signal is an output from the mast er device and an input to slave devices. it is used to synchronize the transfer of data between the mast er and slave on the mosi and miso lines. spi0 gen - erates this signal when operating as a master. the sck signal is ignored by a spi slave when the slave is n ot selected (nss = 1) in 4-wire slave mode. 18.1.4. slave select (nss) the function of the slave-select (nss) signal is dependent on the setting of the nssmd1 and nssmd0 bits in the spi0cn register. there are three possib le modes that can be selected with these bits: 1. nssmd[1:0] = 00: 3-wire master or 3-wire slave mode: spi0 operates in 3-wire mode, and nss is disabled. when operating as a slave dev ice, spi0 is always selected in 3-wire mode. since no select signal is present, spi0 must be the only slave on the bus in 3-wire mode. this is intended for point-to-point communica tion between a master and one slave. 2. nssmd[1:0] = 01: 4-wire slave or multi-ma ster mode: spi0 operates in 4-wire mode, and nss is enabled as an input. when operating as a slave, nss selects the spi0 device. when operating as a master, a 1-to-0 transition of th e nss signal disables t he master function of spi0 so that multiple master devices can be used on the same spi bus. 3. nssmd[1:0] = 1x: 4-wire master mode: spi0 oper ates in 4-wire mode, and nss is enabled as an output. the setting of nssm d0 determines what logic leve l the nss pin will output. this configuration should only be used wh en operating spi0 as a master device. see figure 18.2 , figure 18.3 , and figure 18.4 for typical connection diagra m s of the various operational modes. note that the setting of nssmd bits affects the pinout of the device. when in 3-wire master or 3-wire slave mode, the nss pin will not be mapped by the crossbar. in all other modes, the nss signal will be mapped to a pin on the device. see section ?14. port input/output? on page 126 for general purpose port i/o and crossbar information.
rev. 1.4 197 c8051f320/1 18.2. spi0 master mode operation a spi master device initiates all data transfers on a spi bus. spi0 is placed in master mode by setting the master enable flag (msten, spi0cn.6). writing a byte of data to the spi0 data register (spi0dat) when in master mode writes to the transmit buffer. if the spi shift register is empty, the byte in the transmit buffer is moved to the shift register, and a data transfer begins. the spi0 master immediately shifts out the data serially on the mosi line while provid ing the serial clock on sck. the spi f (spi0cn.7) flag is set to logic 1 at the end of the transfer. if interrupts are enabl ed, an interrupt request is generated when the spif flag is set. while the spi0 master transf ers data to a slave on the mosi line, the addressed spi slave device simultaneously transfers the contents of its shift register to the spi master on the miso line in a full-duplex operation. therefore, the spif flag serves as both a transmit-complete and receive-data-ready flag. the data byte received from the slave is transferred msb-fi rst into the master's shift register. when a byte is fully shifted into the register, it is moved to the receive buffer where it can be read by the processor by reading spi0dat. when configured as a master, spi0 can operate in one of thr ee different modes: multi-master mode, 3-wire single-master mode, and 4-wire single-master mode. the default, multi-master mode is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in this mode, nss is an input to the device, and is used to disable the master spi0 when another mast er is accessing the bus. when nss is pulled low in this mode, msten (spi0cn.6) and spien (spi0cn.0) are set to 0 to disable the spi master device, and a mode fault is generate d (modf, spi0cn.5 = 1). mode fault will gen erate an inte rrupt if enabled. spi0 must be manually re-enabled in soft ware under these circumstances. in multi-master systems, devices will typically default to being slave devices while they are not acting as the system master device. in multi-mas - ter mode, slave devices can be addressed individua lly (if ne eded) using general-purpose i/o pins. figure 18.2 shows a connection diagram between two ma ster devic es in mu ltiple-master mode. 3-wire single-master mode is active when nssmd1 (s pi0cn.3) = 0 and nssmd0 ( spi0cn.2) = 0. in this mode, nss is not used, and is not mapped to an exte rnal port pin through the crossbar. any slave devices that must be addressed in this mode should be selected using general-purpose i/o pins. figure 18.3 shows a connection diagram between a master dev ice in 3- wire master mode and a slave device. 4-wire single-master mode is active when nssmd1 (spi0cn.3) = 1. in this mode, nss is configured as an output pin, and can be used as a slave-select signal for a single spi dev ice. in this mode, the output value of nss is controlled (in software) with the bit nssm d0 (spi0cn.2). additional slave devices can be addressed using general-purpose i/o pins. figure 18.4 shows a connection diagram for a master device in 4-wire master mode and two slave devices.
slave device master device mosi miso sck miso mosi sck slave device master device mosi miso sck miso mosi sck nss nss gpio slave device mosi miso sck nss 18.3. spi0 slave mode operation when spi0 is enabled and not confi gured as a master, it will operate as a spi slave. as a slave, bytes are shifted in through the mosi pin a nd out through the miso pin by a ma ster device controlling the sck sig - nal. a bit counter in the spi0 logic counts sck edges. when 8 bits have been shifted through the shift reg - ister, the spif flag is set to logic 1, and the byte is co pied into the receive buffer. data is read from the receive buffer by reading spi0dat. a slave device cannot initiate transfers. data to be transferred to the master device is pre-loaded into the shift register by writing to spi0dat. writes to spi0dat are double- buffered, and are placed in the transmit buffer first. if the shift register is empty, the contents of the transmit buffer will immediately be transferred into the shift register. when the sh ift register already contains data, the spi will load the shift register wi th the transmit buffer?s contents af ter the last sck edg e of the next (or current) spi transfer. master device 2 master device 1 mosi miso sck miso mosi sck nss gpio nss gpio c8051f320/1 198 rev. 1.4 figure 18.2. multiple-master mode connect ion diagram figure 18.3. 3-wire single master and slave mode connection diagram figure 18.4. 4-wire singl e master mode and 4-wi re slave mode connection diagram
rev. 1.4 199 c8051f320/1 when configured as a slave, spi0 can be configured for 4-wire or 3-wire operation. the default, 4-wire slave mode, is active when nssmd1 (spi0cn.3) = 0 and nssmd0 (spi0cn.2) = 1. in 4-wire mode, the nss signal is routed to a port pin and configured as a digital input. spi0 is enabl ed when nss is logic 0, and disabled when nss is logic 1. the bit counter is reset on a falling edge of n ss. note that the nss sig - nal must be driven low at least 2 system clocks before th e first active edge of sck for each byte transfer. figure 18.4 shows a connection diagram between two slav e de vices in 4-wire slave mode and a master device. 3-wire slave mode is active when nssmd1 (spi0cn. 3) = 0 and nssmd0 (spi0cn.2) = 0. nss is not used in this mode, and is not mapped to an external port pin through the crossbar. since there is no way of uniquely addressing the device in 3-wire slave mode , spi0 must be the only slav e device present on the bus. it is important to note that in 3-wire slave mode there is no external means of resetting the bit counter that determines when a full byte has been received. th e bit counter can only be reset by disabling and re- enabling spi0 with the spien bit. figure 18.3 shows a connection diagram between a slave device in 3- wire slave mode and a master device. 18.4. spi0 interrupt sources when spi0 interrupts are e nabled, the following four flags will gener ate an interrupt when they are set to logic 1: note that all of the following bits must be cleared by software. 1. the spi interrupt flag, spif (spi0cn.7) is set to logi c 1 at the end of each byte transfer. this flag can occur in all spi0 modes. 2. the write collision flag, wcol (spi0cn.6) is set to logic 1 if a write to spi0dat is attempted when the transmit buffer has not been emptied to the spi shift register. when this occurs, the write to spi0dat will be ignored, and the transmi t buffer will not be written.this flag can occur in all spi0 modes. 3. the mode fault flag modf (spi0cn.5) is set to logic 1 when spi0 is configured as a master, a nd for multi-master mode and the nss pin is pulled low. when a mode fault occurs, the msten and spien bits in spi0cn are set to logi c 0 to disable spi0 and allow another master device to access the bus. 4. the receive overrun flag rxovrn (spi0cn.4) is se t to logic 1 when configured as a slave, and a transfer is completed and the receive buffer still holds an unread byte from a previous transfer. the new byte is not transferred to the receive buffer, allowing the previously received data byte to be read. the data byte which caused the overrun is lost. 18.5. serial clock timing four combinations of serial clock phase and polarity can be selected using the clock control bits in the spi0 configuration register (spi0cfg). the ckpha bit ( spi0cfg.5) selects one of two clock phases (edge used to latch the data). the ckpol bit (spi0cfg.4) selects between an active-high or active-low clock. both master and slave devices must be config ured to use the same clock phase and polarity. spi0 should be disabled (by clearing the spien bit, spi0cn.0) when changing the clock phase or polarity. the clock and data line relationships for master mode are shown in figure 18.5 . for slave mode, the clock and data relationships are shown in figure 18.6 and figure 18.7 . note that ckpha must be set to ?0? on both the master and slave spi when communicating betw e en two of the following devices: c8051f04x, c8051f06x, c8051f12x, c8051f31x, c8051f32x, and c8051f33x the spi0 clock rate register (spi 0ckr) as shown in figure 18.3 controls the master mode serial clock frequency. this register is ignored when operating in sla ve mode. when the spi is configured as a master, the maximum data transf er rate (bits/sec) is one-h alf the system clock frequency or 12.5 mhz, whichever is
c8051f320/1 200 rev. 1.4 slower. when the spi is configured as a slave, the maximum data transfer rate (bits/sec) for full-duplex operation is 1/10 the system clock frequency, provided that the master issues sck, nss (in 4-wire slave mode), and the serial input data synchronously with t he slave?s system clock. if the master issues sck, nss, and the serial input data asynchronously, the maximum data transfer rate (bits/sec) must be less than 1/10 the system clock frequency. in the special ca se where the master only wants to transmit data to the slave and does not need to receive data from the slave (i.e. half-duplex operation), the spi slave can receive data at a maximum data transfe r rate (bits/sec) of 1/4 the system clock frequency. this is provided that the master issues sck, nss, and the serial input data synchronously with the slave?s system clock. figure 18.5. master mode data/clock timing figure 18.6. slave mode data /clo ck timing (ckpha = 0) sck (ckpol=0, ckpha=0) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=0) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso/mosi nss (must remain high in multi-master mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi sck (ckpol=0, ckpha=0) sck (ckpol=1, ckpha=0)
rev. 1.4 201 c8051f320/1 figure 18.7. slave mode data /clock timing (ckpha = 1) sck (ckpol=0, ckpha=1) sck (ckpol=1, ckpha=1) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 miso nss (4-wire mode) msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mosi
c8051f320/1 202 rev. 1.4 18.6. spi special function registers spi0 is accessed and controlled through four special function registers in the system controller: spi0cn control register, spi0dat data re gister, spi0cfg configuration register, and spi0ckr clock rate register. the four special function registers related to the operation of the spi0 bus are described in the following figures.
rev. 1.4 203 c8051f320/1 sfr definition 18.1. spi0cfg: spi0 configuration bit 7: spibsy: spi busy (read only). this bit is set to logic 1 when a spi transfer is in progress (master or slave mode). bit 6: msten: master mode enable. 0: disable master mode. operate in slave mode. 1: enable master mode. operate as a master. bit 5: ckpha: spi0 clock phase. this bit controls the spi0 clock phase. 0: data centered on first edge of sck period.* 1: data centered on second edge of sck period.* bit 4: ckpol: spi0 clock polarity. this bit controls the spi0 clock polarity. 0: sck line low in idle state. 1: sck line high in idle state. bit 3: slvsel: slave selected flag (read only). this bit is set to logic 1 whenever the nss pin is low indicating spi0 is the selected slave. it is cleared to logic 0 when nss is high (slave not selected). this bit does not indicate the instantaneous value at the nss pin, but ra ther a de-glitched version of the pin input. bit 2: nssin: nss instantaneous pin input (read only). this bit mimics the instantaneous value that is present on the nss port pin at the time that the register is read. this input is not de-glitched. bit 1: srmt: shift register empty (valid in slave mode, read only). this bit will be set to logic 1 when all data has b een transferred in/out of the shift register, and there is no new information available to read from the transmit buffer or write to the receive buffer. it returns to logic 0 when a data byte is transferred to the shift register from the transmit buffer or by a transition on sck. note: srmt = 1 when in master mode. bit 0: rxbmt: receive buffer empty (valid in slave mode, read only). this bit will be set to logic 1 when the receive buffer has been read and contains no new information. if there is new information availabl e in the receive buffer that has not been read, this bit will return to logic 0. note: rxbmt = 1 when in master mode. *note: in slave mode, data on mosi is sampled in the center of each data bit. in master mode, data on miso is sampled one sysclk before the end of each data bit, to provide maximum settling time for the slave device. see table 18.1 for timing parameters. r r/w r/w r/w r r r r reset value spibsy msten ckpha ckpol slvsel nssin srmt rxbmt 00000111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa1
c8051f320/1 204 rev. 1.4 sfr definition 18.2. spi0cn: spi0 control bit 7: spif: spi0 interrupt flag. this bit is set to logic 1 by hardware at the end of a data transfer. if interrupts are enabled, setting this bit causes the cpu to vector to the spi0 interrupt service r outine. this bit is not automatically cleared by hardware. it must be cleared by software. bit 6: wcol: write collision flag. this bit is set to logic 1 by hardware (and gener ates a spi0 interrupt) to indicate that a write to the spi0 data register was attempted while th e transmit buffer already contained data. it must be cleared by software. bit 5: modf: mode fault flag. this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when a master mode collision is detected (nss is low, msten = 1, and nssmd[1:0] = 01). th is bit is not auto- matically cleared by hardware. it must be cleared by software. bit 4: rxovrn: receive overrun flag (slave mode only). this bit is set to logic 1 by hardware (and generates a spi0 interrupt) when the receive buf- fer still holds unread data fr om a previous transfer and the last bit of th e current transfer is shifted into the spi0 shift register. this bit is not automatically cleared by hardware. it must be cleared by software. bits 3?2: nssmd1?nssmd0: slave select mode. selects between the followi ng nss operation modes: (see section ?18.2. spi0 master mode operat ion? on page 197 and section ?18.3. spi0 slave mode operation? on page 198). 00: 3-wire slave or 3-wire master mode. nss signal is not routed to a port pin. 01: 4-wire slave or multi-master mode (defaul t). nss is always an input to the device. 1x: 4-wire single-master mode. nss signal is mapped as an output from the device and will assume the value of nssmd0. bit 1: txbmt: transmit buffer empty. this bit will be set to logic 0 when new data ha s been written to the tr ansmit buffer. when data in the transmit buffer is transferred to the spi shift register, this bit will be set to logic 1, indicating that it is safe to writ e a new byte to the transmit buffer. bit 0: spien: spi0 enable. this bit enables/disables the spi. 0: spi disabled. 1: spi enabled. r/w r/w r/w r/w r/w r/w r r/w reset value spif wcol modf rxovrn nssmd1 nssmd0 txbmt spien 00000110 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit addressable sfr address: 0xf8
rev. 1.4 205 c8051f320/1 sfr definition 18.3. spi0ckr: spi0 clock rate bits 7?0: scr7-scr0: spi0 clock rate. these bits determine the frequency of the sc k output when the spi0 module is configured for master mode operation. the sck clock frequency is a divided version of the system clock, and is given in the following equation, where sysclk is the system clock frequency and spi0ckr is the 8-bit value held in the spi0ckr register. for 0 <= spi0ckr <= 255 example: if sysclk = 2 mhz and spi0ckr = 0x04, r/w r/w r/w r/w r/w r/w r/w r/w reset value scr7 scr6 scr5 scr4 scr3 scr2 scr1 scr0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa2 f sck 2000000 241 + ?? ? f sck 200 khz = f sck sysclk 2 spi 0 ckr 1+ ?? ? sfr definition 18.4. spi0d at: spi0 data register bits 7?0: spi0dat: spi0 transmit and receive data. the spi0dat register is used to transmit an d receive spi0 data. writing data to spi0dat places the data into the transmit buffer and initiates a transfer when in master mode. a read of spi0dat returns the contents of the receive buffer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xa3
c8051f320/1 206 rev. 1.4 figure 18.8. spi master timing (ckpha = 0) figure 18.9. spi master timing (ckpha = 1) sck* t mckh t mckl mosi t mis miso * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mih sck* t mckh t mckl miso t mih mosi * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t mis
rev. 1.4 207 c8051f320/1 figure 18.10. spi slave timing (ckpha = 0) figure 18.11. spi slave timing (ckpha = 1) sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t sez t sdz sck* t se nss t ckh t ckl mosi t sis t sih miso t sd t soh * sck is shown for ckpol = 0. sck is the opposite polarity for ckpol = 1. t slh t sez t sdz
c8051f320/1 208 rev. 1.4 table 18.1. spi slave timing parameters parameter description min max units master mode timing* ( see figure 18.8 and figure 18.9 ) t mckh sck high time 1 x t sysclk ? ns t mckl sck low time 1 x t sysclk ? ns t mis miso valid to sck shift edge 1 x t sysclk + 20 ? ns t mih sck shift edge to miso change 0 ? ns slave mode timing* (se e figure 18.10 and figure 18.11 ) t se nss falling to first sck edge 2 x t sysclk ? ns t sd last sck edge to nss rising 2 x t sysclk ? ns t sez nss falling to miso valid ? 4 x t sysclk ns t sdz nss rising to miso high-z ? 4 x t sysclk ns t ckh sck high time 5 x t sysclk ? ns t ckl sck low time 5 x t sysclk ? ns t sis mosi valid to sck sample edge 2 x t sysclk ? ns t sih sck sample edge to mosi change 2 x t sysclk ? ns t soh sck shift edge to miso change ? 4 x t sysclk ns t slh last sck edge to mi so change (ckpha = 1 only) 6 x t sysclk 8 x t sysclk ns *note: t sysclk is equal to one period of the device system clock (sysclk).
rev. 1.4 209 c8051f320/1 19. timers each mcu includes four counter/timers: two are 16-bit counter/timers compatible with those found in the standard 8051, and two are 16-bit auto-reload timer for use with the adc, smbus, usb (frame measure - ments), or for general purpose use. these timers can be use d to measure time intervals, count external events and generate periodic interrupt requests. timer 0 and timer 1 are nearly identical and have four pri - mary modes of operation. timer 2 and timer 3 offer 16-bit and split 8-bit timer functionality with auto- reload. timers 0 and 1 may be clocked by one of five sources, deter mined by the timer mode select bits (t1m- t0m) and the clock scale bits (sca1-sca0). the clock scale bits define a pre-scaled clock from which timer 0 and/or timer 1 may be clocked (see figure 19.3 for pre-scaled clock selection). timer 0/1 may then be configured to use this pre-sc ale d clock signal or th e system clock. timer 2 and t imer 3 may be clocked by the system clock, the system clock divided by 12, or the external oscillator clock source divided by 8. timer 0 and timer 1 may also be operated as counters. when fun ctioning as a counter, a counter/timer register is incremented on each high-to-low transition at the selected input pin (t0 or t1). events with a fre - quency of up to one-fourth the system clock's frequen cy can b e counted. the input signal need not be peri - odic, but it should be held at a gi ve n level for at least two full system cl ock cycles to ensure the level is properly sampled. 19.1. timer 0 and timer 1 each timer is implemented as a 16-bit register acce ssed as two separate bytes: a low byte (tl0 or tl1) and a high byte (th0 or th1). the counter/timer co ntrol register (tcon) is used to enable timer 0 and timer 1 as well as indicate status. timer 0 interrupts ca n be enabled by setting the et0 bit in the ie register ( section ?9.3.5. interrupt register descriptions? on page 90 ); timer 1 interrupts can be enabled by setting the et1 bit in the ie register ( sfr definition 9.7 ). both counter/timers operate in one of four primary modes selected by setting the mode select bits t1m1-t0m0 in the counter/timer mode register (tmod). each timer can be configured independently. each operating mode is described below. 19.1.1. mode 0: 13-bit counter/timer timer 0 and timer 1 operate as 13-bit counter/timers in mode 0. the following describes the configuration and operation of timer 0. however, both timers operat e identically, and timer 1 is configured in the same manner as described for timer 0. the th0 register holds the eight msbs of the 13-bit c oun ter/timer. tl0 holds the five lsbs in bit positions tl0.4-tl0.0. the three upper bits of tl0 (tl0.7-tl0 .5) are indeterminate and should be masked out or ignored when reading. as the 13-bit timer register increments and overflows from 0x1fff (all ones) to 0x0000, the timer overflow flag tf 0 (tcon.5) is set and an interrupt will occur if timer 0 interrupts are enabled. the c/t0 bit (tmod.2) selects the counter/timer's cloc k so urce. when c/t0 is set to logic 1, high-to-low transitions at the selected timer 0 input pin (t 0) increment the timer register (refer to section timer 0 and timer 1 modes: ti m er 2 modes: timer 3 modes: 13-bit counter/timer 16-bit timer with auto-reload 16-bit timer with auto-reload 16-bit counter/timer 8-bit counter/timer with auto-reload two 8-bit timers with auto-reload two 8-bit timers with auto-reload two 8-bit counter/timers (timer 0 only)
c8051f320/1 210 rev. 1.4 ?14.1. priority crossbar decoder? on page 128 for information on selecting and configuring external i/o pins). clearing c/t selects the clock defined by the t0m bit (ckcon.3). when t0m is set, timer 0 is clocked by the system clock. when t0m is cleared, timer 0 is clocked by the source selected by the clock scale bits in ckcon (see figure 19.3 ). setting the tr0 bit (tcon.4) enables the timer when ei th er gate0 (tmod.3) is logic 0 or the input signal /int0 is active as defined by bit in0pl in register int01cf (see figure 8.13 ). setting gate0 to ?1? allows the timer to be controlled by the external input signal /int0 (see section ?9.3.5. interrupt register descrip - tions? on page 90 ), facilitating pulse wid th measurement s. setting tr0 does not force the timer to re se t. the timer registers should be loaded with the desired initial value before the timer is enabled. tl1 and th1 form the 13-bit register for timer 1 in the same manner as described above for tl0 and th0. timer 1 is configured and controlled using the relevant tcon and tmod bits just as with timer 0. the input signal /int1 is used with timer 1; the /int1 polari ty is defined by bit in1pl in register int01cf (see figure 8.13 ). tclk tl0 (5 bits) th0 (8 bits) tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tr0 0 1 0 1 sysclk pre-scaled clock ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 gate0 /int0 t0 crossbar int01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 in0pl xor figure 19.1. t0 mode 0 block diagram tr0 gate0 /int0 counter/timer 0 x x disabled 1 0 x enabled 1 1 0 disabled 111enabled x = don't care
rev. 1.4 211 c8051f320/1 19.1.2. mode 1: 16-bit counter/timer mode 1 operation is the same as mode 0, except that the counter/timer registers use all 16 bits. the coun - ter/timers are enabled and configured in mode 1 in the same manner as for mode 0. 19.1.3. mode 2: 8-bit counter/timer with auto-reload mode 2 configures timer 0 and timer 1 to operate as 8-bit counter/timers with automatic reload of the start value. tl0 holds the count and th0 holds the reload va lue. when the counter in tl0 overflows from all ones to 0x00, the timer over flow flag tf0 (tcon.5) is set and the counter in tl0 is reloaded from th0. if timer 0 interrupts are enable d, an interrupt will occur when the tf0 flag is set. the reload va lue in th0 is not changed. tl0 must be initialized to the desired va lue before enabling the timer for the first count to be correct. when in mode 2, timer 1 operates identically to timer 0. both counter/timers are enabled and configured in mode 2 in the same manner as mode 0. setting the tr0 bit (tcon.4) enables the timer when either gate0 (tmod.3) is logic 0 or when the input signal /int0 is active as defined by bit in 0pl in register int01cf (see section ?9.3.2. external interrupts? on page 88 for details on the external input signals /int0 and /int1). tclk tmod t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt tl0 (8 bits) reload th0 (8 bits) 0 1 0 1 sysclk pre-scaled clock int01cf i n 1 s l 1 i n 1 s l 0 i n 1 s l 2 i n 1 p l i n 0 p l i n 0 s l 2 i n 0 s l 1 i n 0 s l 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 19.2. t0 mode 2 block diagram
c8051f320/1 212 rev. 1.4 19.1.4. mode 3: two 8-bit counter/timers (timer 0 only) in mode 3, timer 0 is configured as two separate 8-bit counter/timers held in tl0 and th0. the coun - ter/timer in tl0 is controlled using the timer 0 contro l/st a tus bits in tcon and tmod: tr0, c/t0, gate0 and tf0. tl0 can use either the system clock or an ex ternal input signal as its timebase. the th0 register is restricted to a timer function so urced by the system clock or presca led clock. th0 is enabled using the timer 1 run control bit tr1. th0 sets the timer 1 over flow flag tf1 on overflow and thus controls the timer 1 interrupt. timer 1 is inactive in mode 3. when timer 0 is operat ing in mod e 3, timer 1 can be operated in modes 0, 1 or 2, but cannot be clocked by external signals nor set the tf1 flag and generate an interrupt. however, the timer 1 overflow can be used to generate baud ra tes for the smbus and/or ua rt, and/or initiate adc conversions. while timer 0 is operating in mode 3, timer 1 run control is handled through its mode set - tings. to run timer 1 while timer 0 is in m ode 3, set the timer 1 mode as 0, 1, or 2. to disable timer 1, configure it for mode 3. tl0 (8 bits) tmod 0 1 tcon tf0 tr0 tr1 tf1 ie1 it1 ie0 it0 interrupt interrupt 0 1 sysclk pre-scaled clock tr1 th0 (8 bits) t 1 m 1 t 1 m 0 c / t 1 g a t e 1 g a t e 0 c / t 0 t 0 m 1 t 0 m 0 tr0 gate0 in0pl xor /int0 t0 crossbar ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 19.3. t0 mode 3 block diagram
rev. 1.4 213 c8051f320/1 sfr definition 19.1. bit7: tf1: timer 1 overflow flag. set by hardware when timer 1 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 1 interrupt service routine. 0: no timer 1 overflow detected. 1: timer 1 has overflowed. bit6: tr1: timer 1 run control. 0: timer 1 disabled. 1: timer 1 enabled. bit5: tf0: timer 0 overflow flag. set by hardware when timer 0 overflows. this flag can be cleared by software but is auto- matically cleared when the cpu vectors to the timer 0 interrupt service routine. 0: no timer 0 overflow detected. 1: timer 0 has overflowed. bit4: tr0: timer 0 run control. 0: timer 0 disabled. 1: timer 0 enabled. bit3: ie1: external interrupt 1. this flag is set by hardware when an edge/leve l of type defined by it1 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 1 service routine if it1 = 1. when it1 = 0, th is flag is set to ?1? wh en /int1 is active as defined by bit in1pl in register it01cf (see sfr definition 9.13). bit2: it1: interrupt 1 type select. this bit selects whether the co nfigured /int1 interrup t will be edge or level sensitive. /int1 is configured active low or high by the in1pl bit in the it01cf regist er (see sfr definition 9.13). 0: /int1 is level triggered. 1: /int1 is edge triggered. bit1: ie0: external interrupt 0. this flag is set by hardware when an edge/leve l of type defined by it0 is detected. it can be cleared by software but is automatically cleared when the cpu vectors to the external inter- rupt 0 service routine if it0 = 1. when it0 = 0, th is flag is set to ?1? wh en /int0 is active as defined by bit in0pl in register it01cf (see sfr definition 9.13). bit0: it0: interrupt 0 type select. this bit selects whether the co nfigured /int0 interrup t will be edge or level sensitive. /int0 is configured active low or high by the in0pl bit in register it01cf (see sfr definition 9.13). 0: /int0 is level triggered. 1: /int0 is edge triggered. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0x88 tcon: timer control
c8051f320/1 214 rev. 1.4 sfr definition 19.2. bit7: gate1: timer 1 gate control. 0: timer 1 enabled when tr1 = 1 irrespective of /int1 logic level. 1: timer 1 enabled only when tr1 = 1 and /int1 is active as defined by bit in1pl in regis- ter it01cf (see sfr definition 9.13). bit6: c/t1: counter/timer 1 select. 0: timer function: timer 1 incremented by clock defined by t1m bit (ckcon.3). 1: counter function: timer 1 incremented by high-to-low transitions on external input pin (t1). bits5?4: t1m1?t1m0: timer 1 mode select. these bits select the timer 1 operation mode. bit3: gate0: timer 0 gate control. 0: timer 0 enabled when tr0 = 1 irrespective of /int0 logic level. 1: timer 0 enabled only when tr0 = 1 and /int0 is active as defined by bit in0pl in regis- ter it01cf (see sfr definition 9.13). bit2: c/t0: counter/timer select. 0: timer function: timer 0 incremented by clock defined by t0m bit (ckcon.2). 1: counter function: timer 0 incremented by high-to-low transitions on external input pin (t0). bits1?0: t0m1?t0m0: timer 0 mode select. these bits select the timer 0 operation mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value gate1 c/t1 t1m1 t1m0 gate0 c/t0 t0m1 t0m0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x89 t1m1 t1m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 10 mode 2: 8-bit counter/timer with auto- reload 1 1 mode 3: timer 1 inactive t0m1 t0m0 mode 0 0 mode 0: 13-bit counter/timer 0 1 mode 1: 16-bit counter/timer 10 mode 2: 8-bit counter/timer with auto- reload 1 1 mode 3: two 8-bit counter/timers tmod: timer mode
rev. 1.4 215 c8051f320/1 sfr definition 19.3. bit7: t3mh: timer 3 hig h byte clock select. this bit selects the clock supplied to the timer 3 high byte if timer 3 is configured in split 8- bit timer mode. t3mh is ignored if timer 3 is in any other mode. 0: timer 3 high byte uses the clock de fined by the t3xclk bit in tmr3cn. 1: timer 3 high byte uses the system clock. bit6: t3ml: timer 3 low byte clock select. this bit selects the clock supplied to timer 3. if timer 3 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 3 low byte uses the clock de fined by the t3xclk bit in tmr3cn. 1: timer 3 low byte uses the system clock. bit5: t2mh: timer 2 hig h byte clock select. this bit selects the clock supplied to the timer 2 high byte if timer 2 is configured in split 8- bit timer mode. t2mh is ignored if timer 2 is in any other mode. 0: timer 2 high byte uses the clock de fined by the t2xclk bit in tmr2cn. 1: timer 2 high byte uses the system clock. bit4: t2ml: timer 2 low byte clock select. this bit selects the clock supplied to timer 2. if timer 2 is configured in split 8-bit timer mode, this bit selects the clock supplied to the lower 8-bit timer. 0: timer 2 low byte uses the clock de fined by the t2xclk bit in tmr2cn. 1: timer 2 low byte uses the system clock. bit3: t1m: timer 1 clock select. this select the clock source supplied to timer 1. t1m is ignored when c/t1 is set to logic 1. 0: timer 1 uses the clock defined by the prescale bits, sca1-sca0. 1: timer 1 uses the system clock. bit2: t0m: timer 0 clock select. this bit selects the clock source supplied to ti mer 0. t0m is ignored when c/t0 is set to logic 1. 0: counter/timer 0 uses the clock defin ed by the prescale bits, sca1-sca0. 1: counter/timer 0 uses the system clock. bits1?0: sca1?sca0: timer 0/1 prescale bits. these bits control the division of the clock supplied to timer 0 and/or timer 1 if configured to use prescaled clock inputs. r/w r/w r/w r/w r/w r/w r/w r/w reset value t3mh t3ml t2mh t2ml t1m t0m sca1 sca0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8e sca1 sca0 prescaled clock 0 0 system clock divided by 12 0 1 system clock divided by 4 1 0 system clock divided by 48 1 1 external clock divided by 8 note: external clock divided by 8 is synchronized with the system clock. ckcon: clock control
c8051f320/1 216 rev. 1.4 sfr definition 19.4. bits 7?0: tl0: timer 0 low byte. the tl0 register is the low byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8a tl0: timer 0 low byte sfr definition 19.5. bits 7?0: tl1: timer 1 low byte. the tl1 register is the low byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8b tl1: timer 1 low byte sfr definition 19.6. bits 7?0: th0: timer 0 high byte. the th0 register is the high byte of the 16-bit timer 0. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8c th0: timer 0 high byte sfr definition 19.7. bits 7?0: th1: timer 1 high byte. the th1 register is the high byte of the 16-bit timer 1. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x8d th1: timer 1 high byte
rev. 1.4 217 c8051f320/1 19.2. timer 2 timer 2 is a 16-bit timer formed by two 8-bit sfrs: tmr2l (low byte) and tmr2h (high byte). timer 2 may operate in 16-bit auto-reload mode, (split) 8-bit auto -reload mode, or usb start-of-frame (sof) capture mode. the timer 2 operation mode is defined by th e t2split (tmr2cn.3) and t2sof (tmr2cn.4) bits. timer 2 may be clocked by the system clock, the sy stem clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 2 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 19.2.1. 16-bit timer with auto-reload when t2split = ?0? and t2sof = ?0?, timer 2 operates as a 16-bit timer with auto-reload. timer 2 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 2 reload registers (tmr2rlh and tmr2rll) is load ed into the timer 2 register as shown in figure 19.4 , and the timer 2 high byte overflow flag (tmr2cn.7) is se t. if t imer 2 interrupts are enabled (if ie.5 is set), an interrupt will be generat ed on each timer 2 overflow. additiona lly, if timer 2 inte rrupts are enabled and the tf2len bit is set (tmr2cn. 5), an interr upt will be generated each time the lower 8 bits (tmr2l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh reload tclk 0 1 tr2 tmr2cn t2split t2sof tf2l tf2h t2xclk tr2 0 1 t2xclk interrupt tf2len to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 19.4. timer 2 16-bi t mode block diagram
c8051f320/1 218 rev. 1.4 19.2.2. 8-bit timers with auto-reload when t2split = ?1? and t2sof = ?0?, timer 2 operates as two 8-bit timers (tmr2h and tmr2l). both 8- bit timers operate in auto-reload mode as shown in figure 19.5 . tmr2rll holds the reload value for tmr2l; tmr2rlh holds the reload value for tmr2h. the tr2 bit in tmr2cn handles the run control for tm r2 h. tmr2l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sys clk , sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 2 clock select bits (t2mh and t2ml in ckcon) select either sysclk or the clock defined by the timer 2 external cloc k select bit (t2xclk in tmr2cn), as follows: the tf2h bit is set when tmr2h overflows from 0xff to 0x00; the tf2l bit is set when tmr2l overflows from 0xff to 0x00. when timer 2 interrupts are enabled (ie.5), an interrupt is generated each time tmr2h overflows. if timer 2 interrupts are enabled and tf2len (tmr2cn.5) is set, an interrupt is gener - ated each time either tmr2l or tmr2h overflows. wh en tf2len is enabled, software must check the tf2h and tf2l flags to determine the source of the timer 2 interrupt. the tf2h and tf2l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 t2xclk 1 0 tmr2h tmr2rlh reload reload tclk tmr2l tmr2rll interrupt tmr2cn t2split t2sof tf2len tf2l tf2h t2xclk tr2 to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 19.5. timer 2 8- bit mode block diagram t2mh t2xclk tmr2h clock source t2ml t2xclk tmr2l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk
rev. 1.4 219 c8051f320/1 19.2.3. usb start-of-frame capture when t2sof = ?1?, timer 2 operates in usb start-of-frame (sof) capture mode. when t2split = ?0?, tim er 2 counts up and overflows from 0xffff to 0x0000. each time a usb sof is received, the contents of the timer 2 registers (tmr2h:tmr2l) are latched into the timer 2 reload registers ( t mr2rlh:tmr2rll). a timer 2 interrupt is generated if enabled. this mode can be used to calibrate the sys tem clock or external oscillator ag ainst the known usb host sof clock. external clock / 8 sysclk / 12 sysclk tmr2l tmr2h tmr2rll tmr2rlh tclk 0 1 tr2 0 1 interrupt to adc, smbus to smbus tl2 overflow ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m capture usb start-of-frame (sof) enable tmr2cn t f 2 h t f 2 l t 2 x c l k t r 2 t f 2 l e n t 2 s o f t 2 s p l i t figure 19.6. timer 2 sof capt ure mode (t2split = ?0?) when t2split = ?1?, the timer 2 registers (tmr2h and tmr2l) act as two 8-bit counters. each counter coun ts up independently and overflows from 0xff to 0x00. each time a usb sof is received, the contents of the timer 2 registers are latched into the timer 2 reload registers (tmr2rlh and tmr2rll). a ti m er 2 interrupt is generated if enabled. sysclk tclk 0 1 tr2 external clock / 8 sysclk / 12 0 1 1 0 tmr2h tmr2rlh tclk tmr2l tmr2rll to adc, smbus to smbus ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr2cn t f 2 h t f 2 l t 2 x c l k t r 2 t f 2 l e n t 2 s o f t 2 s p l i t usb start-of-frame (sof) capture enable capture interrupt figure 19.7. timer 2 sof capt ure mode (t2split = ?1?)
c8051f320/1 220 rev. 1.4 sfr definition 19.8. bit7: tf2h: timer 2 high byte overflow flag. set by hardware when the timer 2 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 2 over flows from 0xffff to 0x0000. when the timer 2 interrupt is enabled, setting this bit causes the cpu to vector to the timer 2 interrupt service routine. tf2h is not automatically cleared by hardware and must be cleared by software. bit6: tf2l: timer 2 low byte overflow flag. set by hardware when the timer 2 low byte ov erflows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf2len is set and timer 2 interrupts are enabled. tf2l will set when the low byte overflows regardless of the timer 2 mode. this bit is not automat- ically cleared by hardware. bit5: tf2len: timer 2 low byte interrupt enable. this bit enables/disables timer 2 low byte in terrupts. if tf2len is set and timer 2 inter- rupts are enabled, an interrupt will be ge nerated when the low byte of timer 2 overflows. 0: timer 2 low byte interrupts disabled. 1: timer 2 low byte interrupts enabled. bit4: t2sof: timer 2 start-of-frame capture enable 0: sof capture disabled. 1: sof capture enabled. each time a usb sof is received, the contents of the timer 2 reg- isters (tmr2h and tmr2l) are latched into the timer 2 reload registers (tmr2rlh and tmr2rlh), and a timer 2 interrup t is generated (if enabled). bit3: t2split: timer 2 split mode enable. when this bit is set, timer 2 operates as two 8-bit timers with auto-reload. 0: timer 2 operates in 16-bit auto-reload mode. 1: timer 2 operates as two 8-bit auto-reload timers. bit2: tr2: timer 2 run control. this bit enables/disables timer 2. in 8-bi t mode, this bit enables/disables tmr2h only; tmr2l is always enabled in this mode. 0: timer 2 disabled. 1: timer 2 enabled. bit1: unused. read = 0b. write = don?t care. bit0: t2xclk: timer 2 external clock select. this bit selects the external clock source for timer 2. if timer 2 is in 8-bit mode, this bit selects the external oscillator clock source for both timer by tes. however, the timer 2 clock select bits (t2mh and t2ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 2 external clock selection is the system clock divided by 12. 1: timer 2 external clock selection is the external clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf2h tf2l tf2len t2sof t2split tr2 - t2xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xc8 tmr2cn: timer 2 control
rev. 1.4 221 c8051f320/1 sfr definition 19.9. bits 7?0: tmr2rll: timer 2 reload register low byte. tmr2rll holds the low byte of the reload value for timer 2 when operating in auto-reload mode, or the captured value of the tmr2l register in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xca tmr2rll: timer 2 relo ad register low byte sfr definition 19.10. bits 7?0: tmr2rlh: timer 2 reload register high byte. the tmr2rlh holds the high byte of the reload value for timer 2 when operating in auto- reload mode, or the captured value of the tmr2h register in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcb tmr2rlh: timer 2 relo ad register high byte sfr definition 19.11. bits 7?0: tmr2l: timer 2 low byte. in 16-bit mode, the tmr2l register contains the low byte of the 16-bit timer 2. in 8-bit mode, tmr2l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcc tmr2l: timer 2 low byte sfr definition 19.12. bits 7?0: tmr2h: timer 2 high byte. in 16-bit mode, the tmr2h register contains th e high byte of the 16-bit timer 2. in 8-bit mode, tmr2h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xcd tmr2h timer 2 high byte
c8051f320/1 222 rev. 1.4 19.3. timer 3 timer 3 is a 16-bit timer formed by two 8-bit sfrs: tmr3l (low byte) and tmr3h (high byte). timer 3 may operate in 16-bit auto-reload mode, (split) 8-bit auto -reload mode, or usb start-of-frame (sof) capture mode. the timer 3 operation mode is defined by th e t3split (tmr3cn.3) and t3sof (tmr2cn.4) bits. timer 3 may be clocked by the system clock, the sy stem clock divided by 12, or the external oscillator source divided by 8. the external clock mode is ideal for real-time clock (rtc) functionality, where the internal oscillator drives t he system clock while timer 3 (and/or the pca) is clocked by an external preci - sion oscillator. note that the external oscillator source divided by 8 is synchronized with the system clock. 19.3.1. 16-bit timer with auto-reload when t3split (tmr3cn.3) is zero, timer 3 operates as a 16-bit timer with auto-reload. timer 3 can be clocked by sysclk, sysclk divided by 12, or the exte rnal oscillator clock source divided by 8. as the 16-bit timer register increments and overflows from 0xffff to 0x0000, the 16-bit value in the timer 3 reload registers (tmr3rlh and tm3rll) is load ed into the timer 3 register as shown in figure 19.4 , and the timer 3 high byte overflow flag (tmr3cn.7) is se t. if t i mer 3 interrupts are enabled, an interrupt will be generated on each timer 3 overflow. additionally, if timer 3 interrupts are enabled and the tf3len bit is set (tmr3cn.5), an interrupt will be generated each time the lower 8 bits (tmr3l) overflow from 0xff to 0x00. external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh reload tclk 0 1 tr3 tmr3cn t3split t3sof tf3l tf3h t3xclk tr3 0 1 t3xclk interrupt tf3len to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m figure 19.8. timer 3 16-bi t mode block diagram
rev. 1.4 223 c8051f320/1 19.3.2. 8-bit timers with auto-reload when t3split is set, timer 3 operates as two 8-bi t timers (tmr3h and tmr3l). both 8-bit timers oper - ate in auto-reload mode as shown in figure 19.5 . tmr3rll holds the reload va lue for tmr3l; tmr3rlh holds the reload value for tmr3h. the tr 3 bit in tmr3cn handles the run control for tmr3h. tmr3l is always running when configured for 8-bit mode. each 8-bit timer may be c onfigured to use sys clk , sysclk divided by 12, or the external oscillator clock source divided by 8. the timer 3 clock select bits (t3mh and t3ml in ckcon) select either sysclk or the clock defined by the timer 3 external cloc k select bit (t3xclk in tmr3cn), as follows: the tf3h bit is set when tmr3h overflows from 0xff to 0x00; the tf3l bit is set when tmr3l overflows from 0xff to 0x00. when timer 3 interrupts are enabled, an interrupt is generated each time tmr3h over - flows. if timer 3 interrupts are enabled and tf3len (tm r 3cn.5) is set, an interrupt is generated each time either tmr3l or tmr3h overflows. when tf3le n is enabled, software must check the tf3h and tf3l flags to determine the source of the timer 3 interrupt. the tf3h and tf3l interrupt flags are not cleared by hardware and must be manually cleared by software. sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 t3xclk 1 0 tmr3h tmr3rlh reload reload tclk tmr3l tmr3rll interrupt tmr3cn t3split t3sof tf3len tf3l tf3h t3xclk tr3 ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m to adc figure 19.9. timer 3 8- bit mode block diagram t3mh t3xclk tmr3h clock source t3ml t3xclk tmr3l clock source 0 0 sysclk / 12 0 0 sysclk / 12 0 1 external clock / 8 0 1 external clock / 8 1 x sysclk 1 x sysclk
c8051f320/1 224 rev. 1.4 19.3.3. usb start-of-frame capture when t3sof = ?1?, timer 3 operates in usb start-of-frame (sof) capture mode. when t3split = ?0?, tim er 3 counts up and overflows from 0xffff to 0x0000. each time a usb sof is received, the contents of the timer 3 registers (tmr3h:tmr3l) are latched into the timer 3 reload registers ( t mr3rlh:tmr3rll). a timer 3 interrupt is generated if enabled. this mode can be used to calibrate the sys tem clock or external oscillator ag ainst the known usb host sof clock. external clock / 8 sysclk / 12 sysclk tmr3l tmr3h tmr3rll tmr3rlh tclk 0 1 tr3 0 1 interrupt to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m capture usb start-of-frame (sof) enable tmr3cn t f 3 h t f 3 l t 3 x c l k t r 3 t f 3 l e n t 3 s o f t 3 s p l i t figure 19.10. timer 3 sof ca pture mode (t3split = ?0?) when t3split = ?1?, the timer 3 registers (tmr3h and tmr3l) act as two 8-bit counters. each counter coun ts up independently and overflows from 0xff to 0x00. each time a usb sof is received, the contents of the timer 3 registers are latched into the timer 3 reload registers (tmr3rlh and tmr3rll). a ti m er 3 interrupt is generated if enabled. sysclk tclk 0 1 tr3 external clock / 8 sysclk / 12 0 1 1 0 tmr3h tmr3rlh tclk tmr3l tmr3rll to adc ckcon t 3 m h t 3 m l s c a 0 s c a 1 t 0 m t 2 m h t 2 m l t 1 m tmr3cn t f 3 h t f 3 l t 3 x c l k t r 3 t f 3 l e n t 3 s o f t 3 s p l i t usb start-of-frame (sof) capture enable capture interrupt figure 19.11. timer 3 sof capt ure mode (t3split = ?1?)
rev. 1.4 225 c8051f320/1 sfr definition 19.13. bit7: tf3h: timer 3 high byte overflow flag. set by hardware when the timer 3 high byte overflows from 0xff to 0x00. in 16 bit mode, this will occur when timer 3 overflows from 0x ffff to 0x0000. when the timer 3 interrupt is enabled, setting this bit causes the cpu to vector to the timer 3 interrupt service routine. tf3h is not automatically cleared by har dware and must be cleared by software. bit6: tf3l: timer 3 low byte overflow flag. set by hardware when the timer 3 low byte ov erflows from 0xff to 0x00. when this bit is set, an interrupt will be generated if tf3len is set and timer 3 interrupts are enabled. tf3l will set when the low byte overfl ows regardless of the timer 3 mode. this bit is not automat- ically cleared by hardware. bit5: tf3len: timer 3 lo w byte interrupt enable. this bit enables/disables timer 3 low byte in terrupts. if tf3len is set and timer 3 inter- rupts are enabled, an interrupt will be generated when the low byte of timer 3 overflows. this bit should be cleared when operating timer 3 in 16-bit mode. 0: timer 3 low byte interrupts disabled. 1: timer 3 low byte interrupts enabled. bit4: t3sof: timer 3 start-of-frame capture enable 0: sof capture disabled. 1: sof capture enabled. each time a usb sof is received, the contents of the timer 3 reg- isters (tmr3h and tmr3l) are latched into the timer3 reload registers (tmr3rlh and tmr3rlh), and a timer 3 interrupt is generated (if enabled). bit3: t3split: timer 3 split mode enable. when this bit is set, timer 3 operates as two 8-bit timers with auto-reload. 0: timer 3 operates in 16-bit auto-reload mode. 1: timer 3 operates as tw o 8-bit auto-reload timers. bit2: tr3: timer 3 run control. this bit enables/disables timer 3. in 8-bit mode, this bit enables/disables tmr3h only; tmr3l is always enabl ed in this mode. 0: timer 3 disabled. 1: timer 3 enabled. bit1: unused. read = 0b. write = don?t care. bit0: t3xclk: timer 3 external clock select. this bit selects the external clock source for ti mer 3. if timer 3 is in 8-bit mode, this bit selects the external oscillator clock source fo r both timer bytes. however, the timer 3 clock select bits (t3mh and t3ml in register ckcon) may still be used to select between the external clock and the system clock for either timer. 0: timer 3 external clock selection is the system clock divided by 12. 1: timer 3 external clock selection is the extern al clock divided by 8. note that the external oscillator source divided by 8 is synchronized with the system clock. r/w r/w r/w r/w r/w r/w r/w r/w reset value tf3h tf3l tf3len t3sof t3split tr3 - t3xclk 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x91 tmr3cn: timer 3 control
c8051f320/1 226 rev. 1.4 sfr definition 19.14. bits 7?0: tmr3rll: timer 3 reload register low byte. tmr3rll holds the low byte of the reload value for timer 3 when operating in auto-reload mode, or the captured value of the tmr3l r egister when operating in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x92 tmr3rll: timer 3 reload register low byte sfr definition 19.15. bits 7?0: tmr3rlh: timer 3 reload register high byte. the tmr3rlh holds the high byte of the reload value for timer 3 when operating in auto- reload mode, or the captured value of the tmr3h register when operating in capture mode. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x93 tmr3rlh: timer 3 relo ad register high byte sfr definition 19.16. bits 7?0: tmr3l: timer 3 low byte. in 16-bit mode, the tmr3l register contains the low byte of the 16-bit timer 3. in 8-bit mode, tmr3l contains the 8-bit low byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x94 tmr3l: timer 3 low byte sfr definition 19.17. bits 7?0: tmr3h: timer 3 high byte. in 16-bit mode, the tmr3h register contains the high byte of the 16-bit timer 3. in 8-bit mode, tmr3h contains the 8-bit high byte timer value. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0x95 tmr3h timer 3 high byte
rev. 1.4 227 c8051f320/1 20. programmable counter array (pca0) the programmable counter array (pca0) provides enhanced timer functionality while requiring less cpu intervention than the standard 8051 counter/timers. th e pca consists of a dedicated 16-bit counter/timer and five 16-bit capture/compare modules. each capture/compare module has its own associated i/o line (cexn) which is routed through the crossbar to port i/o when enabled (see section ?14.1. priority cross - bar decoder? on page 128 for details on configuring the crossbar). the counter/timer is driven by a pro - grammable timebase that can select between six sour ces: sy stem clock, system clock divided by four, system clock divided by twelve, the external oscillator clock source divided by 8, timer 0 overflow, or an external clock signal on the eci input pin. each capture/compare module may be configured to operate independently in one of six modes: edge-triggered capture, software timer, high-speed output, fre - quency output, 8-bit pwm, or 16-bit pwm (each mode is described in section ?20.2. capture/compare modules? on page 229 ). the external oscillator clock option is id eal for real-time clock (rtc) functionality, allowing the pca to be clocked by a precis ion external osc ill ator while the internal oscillator drives the sys - tem clock. the pca is configured and controlled th ro ugh the system controller's special function regis - ters. the pca block diagram is shown in figure 20.1 . note: the pca module 4 may be used as a watchdog timer (wdt), and is enabled in this mode following a system reset. access to certain pca registers is restricted while wdt mode is enabled. see section 20.3 for details capture/compare module 1 capture/compare module 0 capture/compare module 2 capture/compare module 3 capture/compare module 4 / wdt cex1 eci crossbar cex2 cex3 cex4 cex0 port i/o 16-bit counter/timer pca clock mux sysclk/12 sysclk/4 timer 0 overflow eci sysclk external clock/8 figure 20.1. pca block diagram
c8051f320/1 228 rev. 1.4 20.1. pca counter/timer the 16-bit pca counter/timer consists of two 8-bi t sfrs: pca0l and pca0h. pca0h is the high byte (msb) of the 16-bit counter/timer and pca0l is the lo w byte (lsb). reading pc a0l automatically latches the value of pca0h into a ?snapshot? register; the following pca0h read accesses this ?snapshot? register. reading the pca0l register first guarantees an accu rate reading of the entire 16-bit pca0 counter. reading pca0h or pca0l does not disturb the counte r operation. the cps2-cps0 bits in the pca0md register select the timebase for the counter/timer as shown in ta b l e 20.1 . when the counter/timer ov e r flows from 0xffff to 0x0000, the coun ter overflow flag (cf) in pca0cn is set to logic 1 and an interrupt request is generated if cf interrupts are enabled. setting the ecf bit in pca0md to logic 1 enables the cf flag to generate an interrupt request. the cf bit is not automatically cleared by hardware when the cpu vectors to the in terrupt service routine, and must be cleared by soft - ware (note: pca0 interrupts must be globally enabled before cf interrupts are recognized. pca0 inter - rupts are globally enabled by setting the ea bit (ie.7) an d the epca0 bit in eie1 to logic 1). clearing the cidl bit in the pca0md register a llows the pca to continue normal op eration while the cpu is in idle mode. table 20.1. pca timebase input options *note: external oscillator source divided by 8 is synchr onized with the system clock. pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 idle 0 1 pca0h pca0l snapshot register to sfr bus overflow to pca interrupt system cf pca0l read to pca modules sysclk/12 sysclk/4 timer 0 overflow eci 000 001 010 011 100 101 sysclk external clock/8 figure 20.2. pca counter /timer block diagram cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external oscillator source divided by 8* 1 1 x reserved
rev. 1.4 229 c8051f320/1 20.2. capture/compare modules each module can be configured to operate independently in one of six operation modes: edge-triggered capture, software timer, high speed output, frequency output, 8-bit pulse width modulator, or 16-bit pulse width modulator. each module has special func tion registers (sfrs) asso ciated with it in the cip- 51 system controller. these registers are used to exchange data with a module and configure the module's mode of operation. ta b l e 20.2 summarizes the bit settings in the pca0cpmn registers used to select the pca capture/com - pare module?s operating modes. setting the eccfn bi t in a pca0cpmn register enables the module's ccfn interrupt. note: pca0 interrupts must be globally enabled before individual ccfn interrupts are rec - ognized. pca0 interrupts are globally enabled by se tting the ea bit and the epca0 bit to logic 1. see figure 20.3 for details on the pca interrupt configuration. table 20.2. pca0cpm register settings fo r pca capture/compare modules note: x = don?t care pwm16 ecom capp capn mat tog pwm eccf operation mode x x 10000x capture triggered by positive edge on cexn x x 01000x capture triggered by negative edge on cexn x x 11000x capture triggered by transition on cexn x 1 00100x software timer x 1 00110x high speed output x 1 0 0 x 1 1 x frequency output 0 1 0 0 x 0 1 x 8-bit pulse width modulator 1 1 0 0 x 0 1 x 16-bit pulse width modulator
pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 0 1 pca module 0 (ccf0) pca module 1 (ccf1) eccf1 0 1 eccf0 0 1 pca module 2 (ccf2) eccf2 0 1 pca module 3 (ccf3) eccf3 0 1 pca module 4 (ccf4) eccf4 pca counter/ timer overflow 0 1 interrupt priority decoder epca0 0 1 ea 0 1 pca0cpmn (for n = 0 to 4) p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n c8051f320/1 230 rev. 1.4 figure 20.3. pca interrupt block diagram 20.2.1. edge-triggered capture mode in this mode, a valid transition on the cexn pin ca uses the pca to capture th e value of the pca counter/ timer and load it into the corresponding module's 16-bit capture/compare register (pca0cpln and pca0cphn). the cappn and capnn bits in the pca0cpmn register are used to select the type of transi - tion that triggers the capture: low-to-high transition (p o s itive edge), high-to-low transition (negative edge), or either transition (positive or negative edge). when a capture occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not automatically cleared by hardware when th e cpu vectors to the interrupt service routine, and must be cleared by software . if both cappn and capnn bits are set to logic 1, then the state of the port pin associated with cexn can be read directly to de termine whether a rising-edge or falling-edge caused the capture.
pca0l pca0cpln pca timebase cexn crossbar port i/o pca0h capture pca0cphn 0 1 0 1 (to ccfn) pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt 0 000x x rev. 1.4 231 c8051f320/1 figure 20.4. pca capture mode diagram note: the cexn input sign al must remain high or lo w for at least 2 system clock cycles to be recognized by the hardware.
c8051f320/1 232 rev. 1.4 20.2.2. software timer (compare) mode in software timer mode, the pca c ounter/timer value is compared to the module's 16-bit capture/compare register (pca0cphn and pca0cpln). when a match occurs, the capture/compare flag (ccfn) in pca0cn is set to logic 1 and an interrupt request is generated if ccf interrupts are enabled. the ccfn bit is not autom atica lly cleared by hard ware when the cpu vectors to the interrupt service routine, and must be cleared by software. setting the ecomn and matn bits in the pca0cpmn register enables software timer mode. important note about capture/compare registers : wh en writin g a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 00 00 0 1 x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt figure 20.5. pca software timer mode diagram
rev. 1.4 233 c8051f320/1 20.2.3. high speed output mode in high speed output mode, a module?s associated cexn pin is toggled each time a match occurs between the pca counter and the module's 16- bit capture/compare register (pca0cphn and pca0cpln) setting the togn, matn, and ecomn bits in the pca0cpmn register enables the high- speed output mode. important note about capture/compare registers : wh en writin g a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. match 16-bit comparator pca0h pca0cphn enable pca0l pca timebase pca0cpln 0 1 00 0x enb enb 0 1 write to pca0cpln write to pca0cphn reset pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x cexn crossbar port i/o toggle 0 1 togn pca0cn c f c r c c f 0 c c f 2 c c f 1 c c f 4 c c f 3 pca interrupt figure 20.6. pca high speed output mode diagram
c8051f320/1 234 rev. 1.4 20.2.4. frequency output mode frequency output mode produces a programmable-freq uency square wave on the module?s associated cexn pin. the capture/compare module high byte holds the number of pca clocks to count before the out - put is toggled. the frequency of the square wave is then defined by equation 20.1 . equation 20.1. square wave frequency output f cexn f pca 2 pca0 cphn ? ------------------- --------------------- - = note: a value of 0x00 in the pca0cphn register is equal to 256 for this equation. where f pca is the frequency of the clock selected by the cps2-0 bits in the pca mode register, pca0md. the lower byte of the capture/compare module is co mpared to the pca counter low byte; on a match, cexn is toggled and the offset held in the high byte is added to the matched value in pca0cpln. fre - quency output mode is enabled by setting the ecom n, t o gn, and pwmn bits in the pca0cpmn register. 8-bit comparator pca0l enable pca timebase match pca0cphn 8-bit adder pca0cpln adder enable cexn crossbar port i/o toggle 0 1 togn 000 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n x enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 20.7. pca frequency output mode
rev. 1.4 235 c8051f320/1 20.2.5. 8-bit pulse width modulator mode each module can be used independently to generate a pulse width modulated (pwm) output on its associ - ated cexn pin. the frequency of the output is depe nde nt on the timebase for the pca counter/timer. the duty cycle of the pwm output signal is varied using the module's pca0cpln capture/compare register. when the value in the low byte of the pca counter/ti mer (pca0l) is equal to the value in pca0cpln, the output on the cexn pin will be se t. when the count value in pca0l overflows, the cexn output will be reset (see figure 20.8 ). also, when the counter/timer low byte (pca0l) overflows from 0xff to 0x00, pca0cpln is reloaded automatically w i th the value stored in the module?s capture/compare high byte (pca0cphn) without software intervention. setting t he ecomn and pwmn bits in the pca0cpmn register enables 8-bit pulse width modulator mode. the duty cycle for 8-bit pwm mode is given by equation 20.2 . important note about capture/compare registers : wh en writin g a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. dutycycle 256 pca0 cphn ? ?? 256 ----------------------------------- ---------------- = equation 20.2. 8-bi t pwm duty cycle using equation 20.2 , the largest duty cycle is 100% (pca0cph n = 0) , and the smallest duty cycle is 0.39% (pca0cphn = 0xff). a 0% duty cycle may be g e nerated by clearing the ecomn bit to ?0?. 8-bit comparator pca0l pca0cpln pca0cphn cexn crossbar port i/o enable overflow pca timebase 00x0 x q q set clr s r match pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 0 enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 20.8. pca 8-bi t pwm mode diagram
c8051f320/1 236 rev. 1.4 20.2.6. 16-bit pulse width modulator mode a pca module may also be operated in 16-bit pwm mode. in this mode, the 16-bit capture/compare mod - ule defines the number of pca clocks for the low time of the pwm signal. when the pca counter matches the mod ule contents, the output on cexn is asserted high; when the counter over flows, cexn is asserted low. to output a varying duty cycle, new value wr ites should be synchroniz ed with pca ccfn match inter - rupts. 16-bit pwm mode is enabled by setting the ecom n, pwmn, and pwm16n bits in the pca0cpmn register. for a varying duty cycle, match interrupts should be enabled (eccfn = 1 and matn = 1) to help synchronize the capture/co mpare register writes. the duty cycle for 16-bit pwm mode is given by equation 20.3 . important note about capture/compare registers : wh en writin g a 16-bit value to the pca0 capture/ compare registers, the low byte should always be wri tten first. writing to pca0cpln clears the ecomn bit to ?0?; writing to pca0 cphn sets ecomn to ?1?. equation 20.3. 16-bit pwm duty cycle dutycycle 65536 pca0 cpn ? ?? 65536 ---------------------------------------------------- - = using equation 20.3 , the largest duty cycle is 100% (pca0cpn = 0), an d the smallest duty cycle is 0.0015% (pca0cpn = 0xffff). a 0% duty cycle may be generated by clearing the ecomn bit to ?0?. pca0cpln pca0cphn enable pca timebase 00x0 x pca0cpmn p w m 1 6 n e c o m n e c c f n t o g n p w m n c a p p n c a p n n m a t n 1 16-bit comparator cexn crossbar port i/o overflow q q set clr s r match pca0h pca0l enb enb 0 1 write to pca0cpln write to pca0cphn reset figure 20.9. pca 16-bit pwm mode 20.3. watchdog timer mode a programmable watchdog timer (wdt) function is avai lable through the pca module 4. the wdt is used to generate a reset if the time between writes to th e wdt update register (pca0cph4) exceed a specified limit. the wdt can be configured and enabled/disabled as needed by software. with the wdte and/or wdlck bits set to ?1? in t he pca0m d register, module 4 operates as a watchdog timer (wdt). the module 4 high byte is compared to the pca counter high byte; the module 4 low byte holds the offset to be used wh en wdt updates are performed. the watchdog timer is enabled on reset. writes to some pca registers are restricted while the watchdog timer is enabled.
rev. 1.4 237 c8051f320/1 20.3.1. watchdog timer operation while the wdt is enabled: ? pca counter is forced on. ? writes to pca0l and pca0h are not allowed. ? pca clock source bits (cps2-cps0) are frozen. ? pca idle control bi t ( c idl) is frozen. ? module 4 is forced into watchdog timer mode. ? writes to the module 4 mode register (pca0cpm4) are disabled. while the wdt is enabled, writes to the cr bit will not c h ange the pca counter state; the counter will run until the wdt is disabled. the pca co unter run co ntrol (cr) will read zero if the wdt is enabled but user software has not enabled the pca counter. if a ma tch occurs between pca0cph4 and pca0h while the wdt is enabled, a reset will be gener ated. to prevent a wdt reset, the wdt may be updated with a write of any value to pca0cph4. upon a pca0cph4 write, pca0h plus the offset held in pca0cpl4 is loaded into pca0cph4 (see figure 20.10 ). pca0h enable pca0l overflow reset pca0cpl4 8-bit adder pca0cph4 adder enable pca0md c i d l w d t e e c f c p s 1 c p s 0 w d l c k c p s 2 match write to pca0cph4 8-bit comparator figure 20.10. pca module 4 wi th watchdog timer enabled
c8051f320/1 238 rev. 1.4 note that the 8-bit offset held in pca0cph4 is comp ared to the upper byte of the 16-bit pca counter. this offset value is the number of pca0l overflows before a reset. up to 256 pca clocks may pass before the first pca0l overflow occurs, depending on the valu e of the pca0l when the update is performed. the total offset is then given (in pca clocks) by equation 20.4 , where pca0l is the value of the pca0l register at the time of the update. equation 20.4. watchdog time r offset in pca clocks offset 256 pca0 cpl4 ? ?? 256 pca0 l ? ?? + = the wdt reset is generated when pca0l overflow s while there is a match between pca0cph4 and pca0h. software may force a wdt reset by writing a ?1? to the ccf4 flag (pca0cn.4) while the wdt is enabled. 20.3.2. watchdog timer usage to configure the wdt, perform the following tasks: 1. disable the wdt by writing a ?0? to the wdte bit. 2. select the desired pca clock s our ce (with th e cps2-cps0 bits). 3. load pca0cpl4 with the desi r e d wdt update offset value. 4. configure the pca idle mode (s et cidl if th e wdt should be suspended while the cpu is in idle mode). 5. enable the wdt by setting the wdte bit to ?1?. 6. (optional) lock the wdt (prevent wdt disabl e until t h e next system reset) by setting the wdlck bit to ?1?. 7. write a value to pca0cph4 to reload the wdt. the pca clock source and idle mode select cannot be changed while the wdt is enabled. the watchdog time r is en abled by setting the wdte or wdlck bits in the pca0md register. when wdlck is set, the wdt cannot be disabled until the next system reset. if wdlck is not set, the wdt is disabled by clearing the wdte bit. the wdt is enabled following any rese t. th e pca0 coun ter clock defaults to the system clock divided by 12, pca0l defaults to 0x00, and pca0cpl4 defaults to 0x00. using equation 20.4 , this results in a wdt timeout interval of 256 pca clo ck cyc les (3072 system clock cycles). ta b l e 20.3 lists some example time - out intervals for typical system clocks.
table 20.3. watchdog timer timeout intervals 1 system clock (hz) pca0cpl4 timeout interval (ms) 24,000,000 255 32.8 24,000,000 128 16.5 24,000,000 32 4.2 12,000,000 255 65.5 12,000,000 128 33.0 12,000,000 32 8.4 4,000,000 255 196.6 4,000,000 128 99.1 4,000,000 32 25.3 1,500,000 2 255 524.3 1,500,000 2 128 264.2 1,500,000 2 32 67.6 32,768 255 24,000 32,768 128 12,093.75 32,768 32 3,093.75 notes: 1. assumes sysclk / 12 as the pca clock source, and a pca0l value of 0x00 at the update time. 2. interna l oscillator reset frequency. rev. 1.4 239 c8051f320/1 20.4. register descriptions for pca following are detailed descriptions of the special func tion registers related to the operation of the pca.
c8051f320/1 240 rev. 1.4 sfr definition 20.1. bit7: cf: pca counter/ timer overflow flag. set by hardware when the pca counter/timer overflows from 0xfff f to 0x0000. when the counter/timer overflow (cf) inte rrupt is enabled, setting this bit causes the cpu to vector to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit6: cr: pca counter/timer run control. this bit enables/disables the pca counter/timer. 0: pca counter/timer disabled. 1: pca counter/timer enabled. bit5: unused. read = 0b, write = don't care. bit4: ccf4: pca module 4 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf4 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit3: ccf3: pca module 3 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf3 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit2: ccf2: pca module 2 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf2 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit1: ccf1: pca module 1 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf1 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. bit0: ccf0: pca module 0 capture/compare flag. this bit is set by hardware when a match or capture occurs. when the ccf0 interrupt is enabled, setting this bit causes the cpu to vect or to the pca interrupt service routine. this bit is not automatically cleared by hardware and must be cleared by software. r/w r/w r/w r/w r/w r/w r/w r/w reset value cf cr - ccf4 ccf3 ccf2 ccf1 ccf0 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: (bit addressable) 0xd8 pca0cn: pca control
rev. 1.4 241 c8051f320/1 sfr definition 20.2. bit7: cidl: pca counter /timer idle control. specifies pca behavior wh en cpu is in idle mode. 0: pca continues to function normally while the system controller is in idle mode. 1: pca operation is suspended while t he system controller is in idle mode. bit6: wdte: watchdog timer enable if this bit is set, pca module 4 is used as the watchdog timer. 0: watchdog timer disabled. 1: pca module 4 enabled as watchdog timer. bit5: wdlck: watchdog timer lock this bit enables and locks the watchdog timer. when wdlck is set to ?1?, the watchdog timer may not be disabled until the next system reset. 0: watchdog timer unlocked. 1: watchdog timer enabled and locked. bit4: unused. read = 0b, write = don't care. bits3?1: cps2?cps0: pca coun ter/timer pulse select. these bits select the timebase source for the pca counter . bit0: ecf: pca counter/timer overflow interrupt enable. this bit sets the masking of the pca counter/timer overflow (cf) interrupt. 0: disable the cf interrupt. 1: enable a pca counter/timer overflow interrupt request when cf (pca0cn.7) is set. note: when the wdte bit is set to ?1?, the pca0md register cannot be modified. to change the contents of the pca0md register, the watchdog timer must first be disabled. r/w r/w r/w r/w r/w r/w r/w r/w reset value cidl wdte wdlck - cps2 cps1 cps0 ecf 01000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xd9 cps2 cps1 cps0 timebase 0 0 0 system clock divided by 12 0 0 1 system clock divided by 4 0 1 0 timer 0 overflow 011 high-to-low transitions on eci (max rate = system clock divided by 4) 1 0 0 system clock 1 0 1 external clock divided by 8* 1 1 0 reserved 1 1 1 reserved *note: external oscillator source divided by 8 is synchro nized with the system clock. pca0md: pca mode
c8051f320/1 242 rev. 1.4 sfr definition 20.3. pca0cpmn address: pca0cp m0 = 0xda (n = 0), pca0cpm1 = 0xdb (n = 1), pca0cpm2 = 0xdc (n = 2), pca0cpm3 = 0xdd (n = 3), pca0cpm4 = 0xde (n = 4) bit7: pwm16n: 16-bit pulse width modulation enable. this bit selects 16-bit mode when pulse width modulation mode is enabled (pwmn = 1). 0: 8-bit pwm selected. 1: 16-bit pwm selected. bit6: ecomn: comparator function enable. this bit enables/disables the comparator function for pca module n. 0: disabled. 1: enabled. bit5: cappn: capture positive function enable. this bit enables/disables the positive edge capture for pca module n. 0: disabled. 1: enabled. bit4: capnn: capture negative function enable. this bit enables/disables the negative edge capture for pca module n. 0: disabled. 1: enabled. bit3: matn: match function enable. this bit enables/disables the match function for pca module n. when enabled, matches of the pca counter with a module's capture/compare regi ster cause the ccfn bit in pca0md register to be set to logic 1. 0: disabled. 1: enabled. bit2: togn: toggle function enable. this bit enables/disables the toggle function for pca module n. when enabled, matches of the pca counter with a module's capture/compare regi ster cause the logic level on the cexn pin to toggle. if the pwmn bit is also set to logic 1, the module operates in frequency output mode. 0: disabled. 1: enabled. bit1: pwmn: pulse width modulation mode enable. this bit enables/disables the pwm function fo r pca module n. when enabled, a pulse width modulated signal is output on the cexn pin. 8-bit pwm is used if pwm16n is cleared; 16-bit mode is used if pwm16n is set to logic 1. if the togn bit is also set, the module operates in fre- quency output mode. 0: disabled. 1: enabled. bit0: eccfn: capture/compare flag interrupt enable. this bit sets the masking of the capture/compare flag (ccfn) interrupt. 0: disable ccfn interrupts. 1: enable a capture/compare flag interrupt request when ccfn is set. r/w r/w r/w r/w r/w r/w r/w r/w reset value pwm16n ecomn cappn capnn matn togn pwmn eecfn 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xda, 0xdb, 0xdc, 0xdd, 0xde pca0cpmn: pca capture/compare mode
rev. 1.4 243 c8051f320/1 sfr definition 20.4. bits 7?0: pca0l: pca co unter/timer low byte. the pca0l register holds the low byte (lsb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xf9 pca0l: pca counter/timer low byte sfr definition 20.5. bits 7?0: pca0h: pca co unter/timer high byte. the pca0h register holds the high byte (msb) of the 16-bit pca counter/timer. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfa pca0h: pca count er/timer high byte sfr definition 20.6. pca0cpln address: pca0cpl0 = 0xfb (n = 0), pca0cpl1 = 0xe9 (n = 1), pca0cpl2 = 0xeb (n = 2), pca0cpl3 = 0xed (n = 3), pca0cpl4 = 0xfd (n = 4) bits7?0: pca0cpln: pca capture module low byte. the pca0cpln register holds the low byte (lsb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfb, 0xe9, 0xeb, 0xed, 0xfd pca0cpln: pca capture module low byte
c8051f320/1 244 rev. 1.4 sfr definition 20.7. pca0cphn address: pca0cph0 = 0xfc (n = 0), pca0cph1 = 0xea (n = 1), pca0cph2 = 0xec (n = 2), pca0cph3 = 0xee (n = 3), pca0cph4 = 0xfe (n = 4) bits7?0: pca0cphn: pca capture module high byte. the pca0cphn register holds the high byte (msb) of the 16-bit capture module n. r/w r/w r/w r/w r/w r/w r/w r/w reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 sfr address: 0xfc, 0xea, 0x ec,0xee, 0xfe pca0cphn: pca captur e module high byte
rev. 1.4 245 c8051f320/1 21. c2 interface c8051f320/1 devices include an on-chip silicon labs 2-wire (c2) debug interface to allow flash program - ming and in-system debugging with the production part ins t alled in the end applic ation. the c2 interface uses a clock signal (c2ck) and a bi-directional c2 data signal (c2d) to transfer information between the device and a host system. see the c2 interface specification for details on the c2 protocol. 21.1. c2 interface registers the following describes the c2 registers necessary to perform flash programming through the c2 inter - face. all c2 registers are accessed through the c2 inte r f ace as described in the c2 interface specification. c2 register definition 21.1. bits7?0: the c2add register is accessed via the c2 interface to select the target data register for c2 data read and data write commands. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 address description 0x00 selects the device id register for data read instructions 0x01 selects the revision id register for data read instructions 0x02 selects the c2 flash programming control register for data read/write instructions 0xb4 selects the c2 flash programming data register for data read/write instructions c2add: c2 address c2 register definition 21.2. c2 device id this read-only register returns the 8-bit device id: 0x09 (c8051f320/1). reset value 00001001 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
c8051f320/1 246 rev. 1.4 c2 register definition 21.3. this read-only register returns the 8-bit revision id: 0x01 (revision b). reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 revid: c2 revision id c2 register definition 21.4. bits7?0 fpctl: flash programming control register. this register is used to enable flash programm ing via the c2 interface. to enable c2 flash programming, the following codes must be written in order: 0x02, 0x01. note that once c2 flash programming is ena bled, a system reset must be issued to resume normal operation. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 fpctl: c2 flash programming control c2 register definition 21.5. bits7-0: fpdat: c2 flash programming data register. this register is used to pass flash comm ands, addresses, and data during c2 flash accesses. valid commands are listed below. reset value 00000000 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 code command 0x06 flash block read 0x07 flash block write 0x08 flash page erase 0x03 device erase fpdat: c2 flash programming data
rev. 1.4 247 c8051f320/1 21.2. c2 pin sharing the c2 protocol allows the c2 pins to be shared wi th user functions so that in-system debugging and flash programming functions may be performed. this is possible because c2 co mmunication is typically performed when the device is in the halt state, where all on-chip peripherals and user software are stalled. in this halted state, the c2 interface can safely ?b orrow? the c2ck (/rst) and c2d (p3.0) pins. in most applications, external resistors are required to isolat e c2 interface traffic from the user application. a typi - cal isolation configur at ion is shown in figure 21.1 . c2d c2ck /reset (a) input (b) output (c) c2 interface master c8051fxxx figure 21.1. typical c2 pin sharing the configuration in figure 21.1 assumes the following: 1. the user input (b) cannot change stat e while the t arget device is halted. 2. the /rst pin on the target device is used as an input only. additional resistors may be necessary depending on the specific application.
d ocument c hange l ist revision 1.1 to revision 1.2 ? updated document with rohs compliant information. ? updated ta b l e 3.1, ?global electrical characteristics,? on page 28 . ? updated package drawings in section ?4. pinout and package definitions? on page 30. ? updated figure ?5.4 10-bit adc track and conversion example timing? on page 44 . adc takes 14 sar clocks to convert a sample. ? added max and min values for offset and full scale error in ta b l e 5.1, ?adc0 electrical characteris - tics,? on page 54 . ? updated bias generator specifications in ta b l e 6.1, ?voltage reference electr ica l characteristics,? on page 56. ? added max values for comparator supply current in ta b l e 7.1, ?comparator electr ical char acteri stics,? on page 66 . ? updated section ?8. voltage regulator (reg0)? with decoupling and bypass capacitor requirements. ? updated ta b l e 8.1, ?voltage regulator electrical specifications,? on page 68 . ? updated how to clear the ea bit in section ?9.3. interrupt handler? . ? added ta b l e 11.2, ?flash security summary,? on page 109 . ? added section ?11.4. flash write and erase guidelines? on page 110 . ? updated internal oscillato r suspend mode behav i or in section ?13.1.2. internal oscillator suspend mode? . ? updated oscicn reset value in sfr definition 13.1. ?oscicn: internal o scillator c o ntrol? on page 118 . ? corrected maximum smbu s transfer speed in sec tion ?16. smbus? . ? updated ta b l e 16.4, ?smbus status decoding,? on page 184 . ? - slave transmitter (0101 0xx) ? - slave receiver (0001 00x) ? replaced tables 17.1 though 17.6 with a single table ( ta b l e 17.1, ?timer settings for standard baud rates using the internal osc illator ,? on page 194 ). ? updated wcol bit description in sfr definition 18.2. ?spi0cn: spi0 control? on page 204 . ? updated references to it01cf in sfr definition 19.1. tcon: timer control and sfr definition 19.2. tmod: timer mode . ? added step 7 to watchdog timer usage in section ?20.3.2. watchdog timer usage? . ? changed sample system clock frequencies in ta b l e 20.3, ?watchdog timer timeout intervals 1 ,? on page 239 . ? removed references to boundary scan in section ?21. c2 interface? . ? various formatting fixes. revision 1.2 to revision 1.3 ? removed references to "boundary scan" in the c2 chapter. ? updated package drawings to reflect jedec- st an dard nomenclature and supplier variations. ? relaxed maximum vbus detection input threshold specification in ta b l e 5.1 from 4.0 to 2.9 v. revision 1.3 to revision 1.4 ? updated ta b l e 8.1 on page 68 . ? updated ta b l e 15.2 on page 144 . ? removed usb register definition inmax. ? removed usb register definition outmax. c8051f320/1 248 rev. 1.4
rev. 1.4 249 c8051f320/1 n otes :
c8051f320/1 250 rev. 1.4 c ontact i nformation silicon laboratories inc. 400 west cesar chavez ? austin, tx 78701 ? tel: 1+(512) 416-8500 ? fax: 1+(512) 416-9669 ? toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: ? https://www.silabs.com/support/pages/contacttechnicalsupport.aspx ? and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders the information in this document is believed to be accurate in all respects at the time of publ ication but is subject to change without notice. silicon laboratories assumes no re sponsibility for errors and omissions, and disclaims responsibi lity for any consequen ces resulting from the use of information included herein. additi onally, silicon laboratories assumes no responsibility for the fun ction- ing of undescribed features or parameters. silicon laboratories reserves the right to make change s without further notice. sili con laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpos e, nor does silicon laboratories assume any liabi lity arising out of the application or use of any product or circuit, and specifi cally disclaims any and all liability, including without limitation consequential or incident al damages. silicon laboratories product s are not designed, intended, or authorized for use in applications in tended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a si tuation where personal injury or death may occur. should buyer purchase or use silicon laboratories prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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